SLDS186A March   2012  – July 2016 PGA400-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1. 3.1 Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Overvoltage Protection Characteristics
    6. 6.6  Regulator Characteristics
    7. 6.7  Internal Oscillator and External Crystal Interface Characteristics
    8. 6.8  Sensor Supply Characteristics
    9. 6.9  Temperature Sensor Characteristics
    10. 6.10 Stage 1 Gain Characteristics of the Analog Front End for Resistive Bridge Sensors
    11. 6.11 Stage 2 Gain Characteristics
    12. 6.12 Offset and Offset TC Compensation Characteristics
    13. 6.13 ADC Characteristics
    14. 6.14 OWI Characteristics
    15. 6.15 SPI Characteristics
    16. 6.16 I2C Interface Characteristics
    17. 6.17 Non-Volatile Memory Characteristics
    18. 6.18 GPIO Characteristics
    19. 6.19 DAC1 and DAC2 Output Characteristics
    20. 6.20 Input Capture and Output Compare Port Characteristics
    21. 6.21 Diagnostic Characteristics
    22. 6.22 SPI Timing Requirements
    23. 6.23 I2C Interface Timing Requirements
    24. 6.24 Typical Characteristics
  7. Detailed Description
    1. 7.1  Functional Block Diagram
    2. 7.2  Feature Description
      1. 7.2.1  Overvoltage and Reverse Voltage Protection Block
      2. 7.2.2  Linear Regulators and Bandgap + Current Blocks
      3. 7.2.3  Internal OSC/XTAL I/F Block
      4. 7.2.4  Sensor Voltage Supply Block
        1. 7.2.4.1 VBRG Supply for Resistive Bridge Sensors
        2. 7.2.4.2 ICAP Supply for Capacitive Sensors
      5. 7.2.5  Internal Temperature Block and External Temperature Sensing
        1. 7.2.5.1 Internal Temperature Sensor
        2. 7.2.5.2 External Temperature Sensor
      6. 7.2.6  Using the Analog Front End
      7. 7.2.7  Stage 1 Gain Block
      8. 7.2.8  Self Oscillating Demodulator Block
        1. 7.2.8.1 Configuring the Capacitive Sensor Interface for a Particular Sensor
      9. 7.2.9  Sign Bit Block
      10. 7.2.10 Offset and Offset TC Compensation Blocks
      11. 7.2.11 Stage 2 Gain Block
      12. 7.2.12 ADC Buffer Blocks
        1. 7.2.12.1 Analog to Digital Converter Buffer 1
        2. 7.2.12.2 Analog to Digital Converter Buffer 2
      13. 7.2.13 Sigma Delta Modulator Blocks
        1. 7.2.13.1 Sigma Delta Modulator for AD Converter 1
        2. 7.2.13.2 Sigma Delta Modulator for AD Converter 2
      14. 7.2.14 Decimation Filter Blocks
        1. 7.2.14.1 ADC1 Decimation Filter Blocks
        2. 7.2.14.2 Decimation Filters for AD Converter 2
        3. 7.2.14.3 Accessing the ADC Values for the 8051
      15. 7.2.15 8051 Warp Microprocessor Block
      16. 7.2.16 Digital Interface
      17. 7.2.17 One-Wire Interface (OWI)
        1. 7.2.17.1 Overview of OWI
          1. 7.2.17.1.1 OWI Protocol
            1. 7.2.17.1.1.1 Standard Field Structure
            2. 7.2.17.1.1.2 Frame Structure
            3. 7.2.17.1.1.3 Sync Field
            4. 7.2.17.1.1.4 Command Field
            5. 7.2.17.1.1.5 Data Field(s)
          2. 7.2.17.1.2 OWI Operations
            1. 7.2.17.1.2.1 Write Operation
            2. 7.2.17.1.2.2 Read Operation
          3. 7.2.17.1.3 OWI Commands
            1. 7.2.17.1.3.1 OWI Write Command
            2. 7.2.17.1.3.2 OWI Read Initialization Command
            3. 7.2.17.1.3.3 OWI Read Response Command
            4. 7.2.17.1.3.4 OWI Burst Write Command (EEPROM Cache Access)
            5. 7.2.17.1.3.5 OWI Burst Read Command (EEPROM Cache Access)
          4. 7.2.17.1.4 OWI Communication Error Status
        2. 7.2.17.2 Activating and Deactivating the OWI
          1. 7.2.17.2.1 Activating OWI Communication
          2. 7.2.17.2.2 Deactivating OWI Communication
      18. 7.2.18 SPI
        1. 7.2.18.1 Overview of SPI
        2. 7.2.18.2 SPI Interface Protocol
          1. 7.2.18.2.1 SPI Master to PGA400 Commands
          2. 7.2.18.2.2 PGA400-Q1 to SPI Master Response
          3. 7.2.18.2.3 SPI Command Examples
        3. 7.2.18.3 Clocking Details
      19. 7.2.19 I2C Interface
        1. 7.2.19.1 Overview of I2C Interface
        2. 7.2.19.2 I2C Interface Protocol
        3. 7.2.19.3 Activating the I2C Interface
        4. 7.2.19.4 Clocking Details of I2C Interface
    3. 7.3  Programming and Memory
      1. 7.3.1 OTP Memory
      2. 7.3.2 EEPROM Memory
        1. 7.3.2.1 EEPROM Memory Organization
          1. 7.3.2.1.1 EEPROM Cache
          2. 7.3.2.1.2 Bank 0
          3. 7.3.2.1.3 Banks 1-4
          4. 7.3.2.1.4 Bank 5
          5. 7.3.2.1.5 EEPROM Control and Status Registers (ESFR and Test)
            1. 7.3.2.1.5.1 Digital Interface EEPROM Control Register
            2. 7.3.2.1.5.2 8051W EEPROM Program Register (Used with Bank 0 only)
            3. 7.3.2.1.5.3 Microprocessor Reset/Interface Control Register
            4. 7.3.2.1.5.4 EEPROM Status Register
          6. 7.3.2.1.6 Accessing data from EEPROM Banks
            1. 7.3.2.1.6.1 EEPROM Cache Load Process
          7. 7.3.2.1.7 Programming EEPROM Banks
            1. 7.3.2.1.7.1 Programming Bank 0
          8. 7.3.2.1.8 Programming Banks 1-5
          9. 7.3.2.1.9 CRC Calculation, Validation, and Storage for Banks 1-5
      3. 7.3.3 RAM Memory
      4. 7.3.4 SFR/ESFR Memory
      5. 7.3.5 Test Register Memory
    4. 7.4  General Purpose Input Output (GPIO) Pins
      1. 7.4.1 Setting the GPIO Functions
      2. 7.4.2 GPIO Buffers
    5. 7.5  8051W UART
    6. 7.6  DAC Output
    7. 7.7  Input Capture and Output Compare
      1. 7.7.1 Free Running Timer
      2. 7.7.2 Input Capture
      3. 7.7.3 Output Compare
    8. 7.8  Diagnostics
      1. 7.8.1  Power Supply Diagnostics
      2. 7.8.2  Resistive Bridge Sensor Connectivity Diagnostics
      3. 7.8.3  AFE Diagnostics
      4. 7.8.4  Internal Capacitors for Capacitive Sensor Diagnostics
      5. 7.8.5  DAC Diagnostics
      6. 7.8.6  Harness Open Wire Diagnostics
      7. 7.8.7  EEPROM CRC and Trim Error
      8. 7.8.8  RAM MBIST
      9. 7.8.9  Main Oscillator Watchdog
      10. 7.8.10 Software Watchdog
    9. 7.9  Low-Power Mode
    10. 7.10 Register Maps
      1. 7.10.1 8051W Memory Map
      2. 7.10.2 SFR
        1. 7.10.2.1  I/O PORTS(P0,P1,P2,P3)
        2. 7.10.2.2  Stack Pointer (SP)
        3. 7.10.2.3  Data Pointer (DPTR)
        4. 7.10.2.4  Power Control Register (PCON)
        5. 7.10.2.5  Timer/Counter Control (TCON)
        6. 7.10.2.6  Timer/Counter Mode (TMOD)
        7. 7.10.2.7  Timer/Counter Data (TL0 TL1 TH0 TH1)
        8. 7.10.2.8  UART Control (SCON)
        9. 7.10.2.9  UART Data (SBUF)
        10. 7.10.2.10 Interrupt Enable Register 0 (IE)
        11. 7.10.2.11 Interrupt Enable Register 1 (IE1)
        12. 7.10.2.12 Interrupt Priority Register 0 (IP)
        13. 7.10.2.13 Interrupt Priority Register 1 (IP1)
        14. 7.10.2.14 Program Status Word (PSW)
        15. 7.10.2.15 Accumulator (ACC)
        16. 7.10.2.16 Register (B)
      3. 7.10.3 ESFR
        1. 7.10.3.1  PSMON Diagnostics Status (PSMON1, PSMON2)
        2. 7.10.3.2  AFE Diagnostics Status (AFEDIAG)
        3. 7.10.3.3  CPU Watchdog (CLKDIAG)
        4. 7.10.3.4  Sensor 1 Gain Register (SEN1GAIN)
        5. 7.10.3.5  Sensor 2 Gain Register (SEN2GAIN)
        6. 7.10.3.6  Sensor 1 Offset Register (SEN1OFF1, SEN1OFF2)
        7. 7.10.3.7  Sensor 2 Offset Register(SEN2OFF1, SEN2OFF2)
        8. 7.10.3.8  Capacitive Sensor Settings Register (CAPSEN)
        9. 7.10.3.9  Sensor Control (SENCTRL)
        10. 7.10.3.10 GPIO Strong Output Drive Mode (GPIO_STRG)
        11. 7.10.3.11 CTOV clock Count Register (CTOV_CLK_CNT)
        12. 7.10.3.12 ADC Decimator Output (ADCMSB, ADCLSB)
        13. 7.10.3.13 Load ADC Decimator Shadow Register (LD_DEC)
        14. 7.10.3.14 DAC 1 Register (DAC1MSB, DAC1LSB)
        15. 7.10.3.15 DAC 2 Register (DAC2MSB, DAC2LSB)
        16. 7.10.3.16 Decimator and Low Power Control Register (DECCTRL)
        17. 7.10.3.17 Input Capture/Output Compare Control Register (IC_OC_CTRL)
        18. 7.10.3.18 Input Capture 1 Register (IC1MSB, IC1LSB)
        19. 7.10.3.19 Input Capture 2 Register (IC2MSB, IC2LSB)
        20. 7.10.3.20 Output Compare 1 Register (OC1MSB, OC1LSB)
        21. 7.10.3.21 Input Capture/Output Compare GPIO Register (IC_OC_GPIO)
        22. 7.10.3.22 Output Compare 2 Register (OC2MSB, OC2LSB)
        23. 7.10.3.23 Free Running Timer Shadow Register (FRTMSB, FRTLSB)
        24. 7.10.3.24 Communication Data Buffer (COMBUF)
        25. 7.10.3.25 Digital Interface Control Register (DI_CTRL)
        26. 7.10.3.26 Enable Control Register (EN_CTRL)
        27. 7.10.3.27 Enable Control Register (EN_CTRL2)
        28. 7.10.3.28 RAM MBIST Status Register (RAM_MBIST_ST)
        29. 7.10.3.29 EEPROM Status Register (EE_STATUS)
        30. 7.10.3.30 EEPROM Control Register (EE_CTRL)
      4. 7.10.4 Test Registers
        1. 7.10.4.1  Test MUX Activation Register (TESTMUX_ACT)
        2. 7.10.4.2  Communication Data Buffer (COMBUF_T)
        3. 7.10.4.3  Communication Data Buffer Ready (COMBUF_R)
        4. 7.10.4.4  Analog Test MUX Out Register (AMUX_O)
        5. 7.10.4.5  Digital Test MUX Out Register (DMUX_O)
        6. 7.10.4.6  Analog Test MUX In Register (AMUX_I)
        7. 7.10.4.7  Digital Test MUX In Register (DMUX_I)
        8. 7.10.4.8  EEPROM Access Control Register (EEPROM_A)
        9. 7.10.4.9  Micro/Interface Control Register (MICRO_IF_SEL_T)
        10. 7.10.4.10 OWI Error Status 1 (OWI_ERR_1)
        11. 7.10.4.11 OWI Error Status 2 (OWI_ERR_2)
      5. 7.10.5 8051W Interrupts
        1. 7.10.5.1 Standard Interrupts
        2. 7.10.5.2 Extended Interrupts
          1. 7.10.5.2.1 Interrupt Flag Clear
          2. 7.10.5.2.2 Priority Levels / Interrupt Vectors
          3. 7.10.5.2.3 Interrupt Latency
      6. 7.10.6 8051 Instructions
        1. 7.10.6.1 Addressing Modes
          1. 7.10.6.1.1 Direct Addressing
          2. 7.10.6.1.2 Indirect Addressing
          3. 7.10.6.1.3 Register Addressing
          4. 7.10.6.1.4 Register Specific Addressing
          5. 7.10.6.1.5 Immediate Data
          6. 7.10.6.1.6 Indexed Addressing
        2. 7.10.6.2 Arithmetic Instructions
        3. 7.10.6.3 Logical Instructions
        4. 7.10.6.4 Data Transfers
          1. 7.10.6.4.1 Internal Data Memory
          2. 7.10.6.4.2 External Data Memory
        5. 7.10.6.5 Jump Instructions
          1. 7.10.6.5.1 Unconditional Jumps
          2. 7.10.6.5.2 Subroutine Calls and Returns
          3. 7.10.6.5.3 Conditional Jumps
          4. 7.10.6.5.4 Boolean Instructions
        6. 7.10.6.6 Flags
        7. 7.10.6.7 Instruction Table
  8. Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Resistive Bridge Interface
        1. 8.1.1.1 Capacitive Sensor Interface
  9. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Community Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Orderable Information

1 Features

  • Analog Features
    • Analog Front-End for Resistive Bridge Sensors
    • Self-Oscillating Demodulator for Capacitive Sensors
    • On-Chip Temperature Sensor
    • Programmable Gain
    • 16-Bit, 1-MHz Sigma-Delta Analog-to-Digital Converter for Signal Channel
    • 10-Bit Sigma-Delta Analog-to-Digital Converter for Temperature Channel
    • Two 12-Bit Digital-to-Analog Outputs
  • Digital Features
    • Microcontroller Core
      • 10-MHz 8051 WARP Core
        • 2 Clocks Per Instruction Cycle
      • On-Chip Oscillator
    • Memory
      • 8KB of OTP Memory
      • 89 Bytes of EEPROM
      • 256 Bytes Data SRAM
  • Peripheral Features
    • Serial Peripheral Interface (SPI)
    • Inter-Integrated Circuit (I2C)
    • One-Wire Interface (OWI)
    • Two Input Capture Ports
    • Two Output Compare Ports
    • Software Watchdog Timer
    • Oscillator Watchdog
    • Power Management Control
    • Analog Low-Voltage Detect
  • General Features
    • AEC-Q100 Qualified With the Following Results:
      • Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature
      • Device HBM ESD Classification Level 2
      • Device HBM ESD Classification Level C3B
    • Power Supply: 4.5-V to 5.5-V Operational, –5.5-V to 16-V Absolute Maximum

2 Applications

  • Pressure Sensor-Signal Conditioning
  • Level Sensor-Signal Conditioning
  • Humidity Sensor-Signal Conditioning

3 Description

The PGA400-Q1 device is an interface device for piezoresistive, strain gauge, and capacitive-sense elements. The device incorporates the analog front end (AFE) that directly connects to the sense element and has voltage regulators and an oscillator. The device also includes a sigma-delta analog-to-digital converter (ADC), 8051 WARP core microprocessor, and OTP memory. Sensor compensation algorithms can be implemented in software. The PGA400-Q1 device also includes two digital-to-analog converter (DAC) outputs.

Table 1. Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
PGA400QRHHRQ1VQFN (36)6.00 mm × 6.00 mm
PGA400QYZRQ1WCSP (36)3.65 mm × 3.65 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

3.1 Simplified Schematic

PGA400-Q1 FBD2.png

4 Revision History

Changes from * Revision (March 2012) to A Revision

  • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Application and Implementation section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Added RHH packageGo
  • Added Typical Characteristics sectionGo
  • Added information for RHH package to Detailed Description sectionGo
  • Added Register Maps sectionGo