SBAS334D November   2004  – July 2016 DAC5675A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description Continued
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 AC Electrical Characteristics
    7. 7.7 Digital Specifications
    8. 7.8 Operational Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital Inputs
      2. 8.3.2 Clock Input
      3. 8.3.3 Supply Inputs
      4. 8.3.4 DAC Transfer Function
      5. 8.3.5 Reference Operation
      6. 8.3.6 Analog Current Outputs
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
    6. 12.6 Device Nomenclature
      1. 12.6.1 Definitions of Specifications and Terminology
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • 400MSPS Update Rate
  • LVDS-Compatible Input Interface
  • Spurious-Free Dynamic Range (SFDR) to Nyquist:
    • 69dBc at 70MHz IF, 400MSPS
  • W-CDMA Adjacent Channel Power Ratio (ACPR):
    • 73dBc at 30.72MHz IF, 122.88MSPS
    • 71dBc at 61.44MHz IF, 245.76MSPS
  • Differential Scalable Current Sink Outputs: 2mA to 20mA
  • On-Chip 1.2V Reference
  • Single 3.3V Supply Operation
  • Power Dissipation: 660mW at fCLK = 400MSPS, fOUT = 20MHz
  • Package: 48-Pin HTQFP PowerPad™,
    TJA = 28.8°C/W

2 Applications

  • Cellular Base Transceiver Station Transmit Channel:
    • CDMA: WCDMA, CDMA2000, IS-95
    • TDMA: GSM, IS-136, EDGE/GPRS
    • Supports Single-Carrier and Multicarrier
      Applications
  • Test and Measurement: Arbitrary Waveform Generation
  • Direct Digital Synthesis (DDS)
  • Cable Modem Headend

3 Description

The DAC5675A is a 14-bit resolution high-speed digital-to-analog converter. The DAC5675A is designed for high-speed digital data transmission in wired and wireless communication systems, high-frequency direct-digital synthesis (DDS), and waveform reconstruction in test and measurement applications. The DAC5675A has excellent spurious-free dynamic range (SFDR) at high intermediate frequencies, which makes the DAC5675A well-suited for multicarrier transmission in TDMA- and CDMA-based cellular base transceiver stations (BTSs).

The DAC5675A operates from a single-supply voltage of 3.3 V. Power dissipation is 660 mW at
fCLK = 400 MSPS, fOUT = 70 MHz. The DAC5675A provides a nominal full-scale differential current output of 20mA, supporting both single-ended and differential applications. The output current can be directly fed to the load with no additional external output buffer required. The output is referred to the analog supply voltage AVDD.

The DAC5675A comprises a low-voltage differential signaling (LVDS) interface for high-speed digital data input. LVDS features a low differential voltage swing with a low constant power consumption across frequency, allowing for high-speed data transmission with low noise levels; that is, with low electromagnetic interference (EMI). LVDS is typically implemented in low-voltage digital CMOS processes, making it the ideal technology for high-speed interfacing between the DAC5675A and high-speed low-voltage CMOS ASICs or FPGAs. The DAC5675A current-sink-array architecture supports update rates of up to 400MSPS. On-chip edge-triggered input latches provide for minimum setup and hold times, thereby relaxing interface timing.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DAC5675A PHP (48) 7.00 mm x 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simple Schematic

DAC5675A fbd01_bas334.gif

4 Revision History

Changes from C Revision (March 2005) to D Revision

  • Added ESD Ratings, Recommended Operating Conditions, Thermal Information, Detailed Description section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, Mechanical, Packaging, and Orderable Information sectionGo
  • Changed AVDD to DVDD From: –3.6 to +3.6 To: –0.7 to +0.7 in the Absolute Maximum Ratings Go