JAJSD66A May   2017  – February 2022 SN65HVD1781A-Q1

PRODUCTION DATA  

1. 1 特長
2. 2 アプリケーション
3. 3 概要
4. 4 Revision History
5. 5 Pin Configuration and Functions
6. 6 Specifications
   1. 6.1 Absolute Maximum Ratings
   2. 6.2 ESD Ratings—AEC
   3. 6.3 ESD Ratings—IEC
   4. 6.4 Recommended Operating Conditions
   5. 6.5 Thermal Information
   6. 6.6 Electrical Characteristics
   7. 6.7 Power Dissipation Ratings
   8. 6.8 Switching Characteristics
   9. 6.9 Typical Characteristics
7. 7 Parameter Measurement Information
8. 8 Detailed Description
   1. 8.1 Overview
   2. 8.2 Functional Block Diagram
   3. 8.3 Feature Description
      1. 8.3.1 Receiver Failsafe
      2. 8.3.2 Hot-Plugging
   4. 8.4 Device Functional Modes
9. 9 Application and Implementation
   1. 9.1 Application Information
   2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
         1. 9.2.1.1 Data Rate and Bus Length
         2. 9.2.1.2 Bus Loading
      2. 9.2.2 Detailed Design Procedure
         1. 9.2.2.1 Stub Length
         2. 9.2.2.2 Receiver Failsafe
      3. 9.2.3 Application Curve
10. 10Power Supply Recommendations
11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
12. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Documentation Support
       1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
13. 13Mechanical, Packaging, and Orderable Information