JAJSGG2A October   2018  – January 2019 ADS125H01 , ADS125H02

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      機能ブロック図
  4. 改訂履歴
  5. 概要(続き)
  6. Pin Configuration and Functions
    1.     Pin Functions: ADS125H01
    2.     Pin Functions: ADS125H02
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
  8. Parameter Measurement Information
    1. 8.1 Noise Performance
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Analog Inputs
        1. 9.3.1.1 ESD Diodes
        2. 9.3.1.2 Input Multiplexer
      2. 9.3.2  Temperature Sensor
      3. 9.3.3  High-Voltage Power-Supply Readback
      4. 9.3.4  Internal VCOM Connection (Default)
      5. 9.3.5  Programmable Gain Amplifier (PGA)
        1. 9.3.5.1 PGA Input Range
        2. 9.3.5.2 PGA Monitor
      6. 9.3.6  Reference Voltage
        1. 9.3.6.1 Internal Reference
        2. 9.3.6.2 External Reference
        3. 9.3.6.3 AVDD Power-Supply Reference
        4. 9.3.6.4 Reference Monitor
      7. 9.3.7  Current Sources (IDAC1 and IDAC2)
      8. 9.3.8  General-Purpose Inputs and Outputs (GPIOs)
      9. 9.3.9  ADC Modulator
      10. 9.3.10 Digital Filter
        1. 9.3.10.1 Sinc Filter Mode
          1. 9.3.10.1.1 Sinc Filter Frequency Response
        2. 9.3.10.2 FIR Filter
        3. 9.3.10.3 50-Hz and 60-Hz Normal Mode Rejection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Conversion Control
        1. 9.4.1.1 Continuous-Conversion Mode
        2. 9.4.1.2 Pulse-Conversion Mode
        3. 9.4.1.3 Conversion Latency
        4. 9.4.1.4 Start-Conversion Delay
      2. 9.4.2 Chop Mode
      3. 9.4.3 AC-Excitation Mode
      4. 9.4.4 Clock Mode
      5. 9.4.5 Reset
        1. 9.4.5.1 Power-On Reset
        2. 9.4.5.2 Reset by Pin
        3. 9.4.5.3 Reset by Command
      6. 9.4.6 Calibration
        1. 9.4.6.1 Offset and Full-Scale Calibration
          1. 9.4.6.1.1 Offset Calibration Registers
          2. 9.4.6.1.2 Full-Scale Calibration Registers
        2. 9.4.6.2 Offset Calibration (OFSCAL)
        3. 9.4.6.3 Full-Scale Calibration (GANCAL)
        4. 9.4.6.4 Calibration Command Procedure
        5. 9.4.6.5 User Calibration Procedure
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Chip-Select Pins (CS1 and CS2)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Data Input (DIN)
        4. 9.5.1.4 Data Output/Data Ready (DOUT/DRDY)
      2. 9.5.2 Data Ready (DRDY)
        1. 9.5.2.1 DRDY in Continuous-Conversion Mode
        2. 9.5.2.2 DRDY in Pulse-Conversion Mode
        3. 9.5.2.3 Data Ready by Software Polling
      3. 9.5.3 Conversion Data
        1. 9.5.3.1 Main Status Byte (STATUS0)
        2. 9.5.3.2 Conversion Data Format
      4. 9.5.4 Cyclic Redundancy Check (CRC)
      5. 9.5.5 Commands
        1. 9.5.5.1  General Command Format
        2. 9.5.5.2  NOP Command
        3. 9.5.5.3  RESET Command
        4. 9.5.5.4  START Command
        5. 9.5.5.5  STOP Command
        6. 9.5.5.6  RDATA Command
        7. 9.5.5.7  OFSCAL Command
        8. 9.5.5.8  GANCAL Command
        9. 9.5.5.9  RREG Command
        10. 9.5.5.10 WREG Command
        11. 9.5.5.11 LOCK Command
        12. 9.5.5.12 UNLOCK Command
    6. 9.6 Register Map
      1. 9.6.1  Device Identification (ID) Register (address = 00h) [reset = xxh]
        1. Table 31. ID Register Field Descriptions
      2. 9.6.2  Main Status (STATUS0) Register (address = 01h) [reset = 01h]
        1. Table 32. STATUS0 Register Field Descriptions
      3. 9.6.3  Mode 0 (MODE0) Register (address = 02h) [reset = 24h]
        1. Table 33. MODE0 Register Field Descriptions
      4. 9.6.4  Mode 1 (MODE1) Register (address = 03h) [reset = 01h]
        1. Table 34. MODE1 Register Field Descriptions
      5. 9.6.5  Mode 2 (MODE2) Register (address = 04h) [reset = 00h]
        1. Table 35. MODE2 Register Field Descriptions
      6. 9.6.6  Mode 3 (MODE3) Register (address = 05h) [reset = 00h]
        1. Table 36. MODE3 Register Field Descriptions
      7. 9.6.7  Reference Configuration (REF) Register (address = 06h) [reset = 05h]
        1. Table 37. REF Register Field Descriptions
      8. 9.6.8  Offset Calibration (OFCALx) Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
        1. Table 38. OFCAL0, OFCAL1, OFCAL2 Registers Field Description
      9. 9.6.9  Full-Scale Calibration (FSCALx) Registers (address = 0Ah, 0Bh, 0Ch) [reset = 00h, 00h, 40h]
        1. Table 39. FSCAL0, FSCAL1, FSCAL2 Registers Field Description
      10. 9.6.10 Current Source Multiplexer (I_MUX) Register (address = 0Dh) [reset = FFh]
        1. Table 40. I_MUX Register Field Descriptions
      11. 9.6.11 Current Source Magnitude (I_MAG) Register (address = 0Eh) [reset = 00h]
        1. Table 41. I_MAG Register Field Descriptions
      12. 9.6.12 Reserved (RESERVED) Register (address = 0Fh) [reset = 00h]
        1. Table 42. RESERVED Register Field Descriptions
      13. 9.6.13 MODE4 (MODE4) Register (address = 10h) [reset = 50h]
        1. Table 43. MODE4 Register Field Descriptions
      14. 9.6.14 PGA Alarm (STATUS1) Register (address = 11h) [reset = xxh]
        1. Table 44. STATUS1 Register Field Descriptions
      15. 9.6.15 Status 2 (STATUS2) Register (address = 12h) [reset = 0xh]
        1. Table 45. STATUS2 Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Input Range
      2. 10.1.2 Input Overload
        1. 10.1.2.1 Input Signal Rate of Change (dV/dt)
      3. 10.1.3 Unused Inputs and Outputs
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
    3. 10.3 Initialization Setup
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Decoupling
    2. 11.2 Analog Power-Supply Clamp
    3. 11.3 Power-Supply Sequencing
    4. 11.4 5-V to ±15-V DC-DC Converter
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

特長

  • 入力範囲が広い 24 ビットのデルタ・シグマ ADC
  • 入力インピーダンス 1GΩ の PGA
  • プログラム可能な入力範囲:±20mV~±20V
  • 絶対入力電圧範囲:±15.5V
  • 高性能:
    • 同相除去比:100dB
    • オフセット・ドリフト:5nV/°C
    • ゲイン・ドリフト:1ppm/°C
    • INL: 2ppmFSR
  • データ・レートをプログラム可能:2.5SPS~40000SPS
  • 2.5V の外部または内部リファレンス動作
  • 50Hz/60Hz 同時除去モード
  • 信号および基準電圧モニタ
  • 巡回冗長性検査 (CRC)
  • センサ励起電流源 (H02)
  • 外部マルチプレクサ駆動 GPIO (H02)
  • 5mm × 5mm VQFN パッケージ