SLWS207B May   2008  – January 2016 ADS5560 , ADS5562

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  AC Electrical Characteristics for ADS5560 Fs = 40 MSPS
    7. 6.7  AC Electrical Characteristics for ADS5562, Fs = 80 MSPS
    8. 6.8  Electrical Characteristics for ADS5562
    9. 6.9  Electrical Characteristics for ADS5560
    10. 6.10 Digital Characteristics
    11. 6.11 Timing Characteristics for LVDS and CMOS Modes
    12. 6.12 Serial Interface Timing Characteristics
    13. 6.13 Reset Timing
    14. 6.14 Timing Characteristics at Lower Sampling Frequencies
    15. 6.15 Typical Characteristics
      1. 6.15.1 ADS5562 - 80 MSPS
      2. 6.15.2 ADS5560 - 40 MSPS
      3. 6.15.3 Valid Up to Max Clock Rate (ADS5562 or ADS5560)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low-Frequency Noise Suppression
      2. 7.3.2 Analog Input Circuit
        1. 7.3.2.1 Drive Circuit Recommendations
        2. 7.3.2.2 Example Driving Circuit
        3. 7.3.2.3 Input Common-Mode
        4. 7.3.2.4 Programmable Fine Gain
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Sampling Frequency Operation
      2. 7.4.2 Clock Input
        1. 7.4.2.1 Power-Down
          1. 7.4.2.1.1 Global STANDBY
          2. 7.4.2.1.2 Output Buffer Disable
          3. 7.4.2.1.3 Input Clock Stop
        2. 7.4.2.2 Power Supply Sequence
      3. 7.4.3 Output Interface
        1. 7.4.3.1 DDR LVDS Outputs
        2. 7.4.3.2 LVDS Buffer Current Programmability
        3. 7.4.3.3 LVDS Buffer Internal Termination
        4. 7.4.3.4 Parallel CMOS
        5. 7.4.3.5 Output Clock Position Programmability
      4. 7.4.4 Output Data Format
      5. 7.4.5 Reference
        1. 7.4.5.1 Internal Reference
        2. 7.4.5.2 External Reference
    5. 7.5 Programming
      1. 7.5.1 Device Programming Modes
      2. 7.5.2 Using Parallel Interface Control Only
        1. 7.5.2.1 Using Serial Interface Programming Only
        2. 7.5.2.2 Using Both Serial Interface And Parallel Controls
        3. 7.5.2.3 Description of Parallel Pins
      3. 7.5.3 Serial Interface
      4. 7.5.4 Register Initialization
    6. 7.6 Register Maps
      1. 7.6.1 Register Description
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Clocking Source for ADC5562
        2. 8.2.2.2 Amplifier Selection
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Supply Decoupling
      2. 10.1.2 Exposed Thermal Pad
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

    Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low -frequency value.
    Aperture Delay The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs.
    Aperture Jitter The sample-to-sample variation in aperture delay.
    Clock Pulse Width/Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
    Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs
    Effective Number of Bits (ENOB) The ENOB is a measure of a converter’s performance as compared to the theoretical limit based on quantization noise.
    Equation 8. ADS5560 ADS5562 q5_enob_lws183.gif
    Gain Error The gain error is the deviation of the ADC’s actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range.
    Integral Nonlinearity (INL) The INL is the deviation of the ADC’s transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs.
    Maximum Sample Rate The maximum conversion rate at which certified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted.
    Minimum Sample Rate The minimum conversion rate at which the ADC functions.
    Offset Error The offset error is the difference, given in number of LSBs, between the ADC’s actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV.
    Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding DC.
    SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the full-scale range of the converter.
    Equation 9. ADS5560 ADS5562 q4_sinad_lws183.gif
    Signal-to-Noise Ratio SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at DC and the first nine harmonics.
    SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the full-scale range of the converter.
    Equation 10. ADS5560 ADS5562 q3_snr_lws183.gif
    Spurious-Free Dynamic Range (SFDR) The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
    Temperature Drift The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation of the parameter across the TMIN to TMAX range by the difference TMAX–TMIN.
    Total Harmonic Distortion (THD) THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD).
    Equation 11. ADS5560 ADS5562 q6_thd_lws183.gif

    THD is typically given in units of dBc (dB to carrier).

    Two-Tone Intermodulation Distortion IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at either frequency 2f1–f2 or 2f2–f1. IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range.
    Voltage Overload Recovery The number of clock cycles taken to recover to less than 1% error for a 6-dB overload on the analog inputs.

11.2 Documentation Support

11.2.1 Related Documentation

  • ADS5560/62EVM User's Guide, SLAU260
  • ADS6149EVM User's Guide, SLWU061
  • ADS5547 14-BIT, 210 MSPS ADC With DDR LVDS/CMOS Outputs, SLWS192
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters, SCAA902
  • CDCE72010 Phase Noise Performance and Jitter Cleaning Ability, SCAA091
  • Design Considerations for Avoiding Timing Errors During High-Speed ADC, LVDS Data Interface with FPGA, SLAA592
  • Driving High-Speed, Analog-to-Digital Converters - Part I, Circuit Topologies and System-Level Parameters, SLAA416
  • QFN Layout Guidelines, SLOA122
  • QFN/SON PCB Attachment , SLUA271
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio, SLAA407
  • Why Oversample When Undersampling Can Do The Job? , SLAA594

11.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.

Table 21. Related Links

PARTS PRODUCT FOLDER SAMPLE AND BUY TECHNICAL DOCUMENTS TOOLS AND SOFTWARE SUPPORT AND COMMUNITY
ADS5560 Click here Click here Click here Click here Click here
ADS5562 Click here Click here Click here Click here Click here

11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.5 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.