8.2.1 Design Requirements

To begin the design process, a few parameters must be decided upon. The designer must know the following:

• Output range of the potential transformers (elements labeled PT1, PT2, and PT3 in Figure 43)
• Output range of the current transformers (elements labeled CT1, CT2, and CT3 in Figure 43)
• Input impedance required from the analog front-end for each channel
• Fundamental frequency of the power system
• Number of harmonics that must be acquired
• Type of signal conditioning required from the analog front end for each channel

8.2.2 Detailed Design Procedure

Figure 44 shows the topology chosen to meet the design requirements. A feedback capacitor C_F is included to provide a low-pass filter characteristic and attenuate signals outside the band of interest.

Figure 44. Operational Amplifier in an Inverting Configuration

The potential transformers (PTs) and current transformers (CTs) used in the system depicted in Figure 43 provide the six input variables required. These transformers have a ±10-V output range. Although the PTs and CTs provide isolation from the power system, the value of R_IN is selected as 100 kΩ to provide an additional, high-impedance safety element to the input of the ADC. Moreover, selecting a low-frequency gain of –1 V/V (as shown in Equation 5) provides a ±10-V output that can be fed into the ADS8556 device; therefore, the value of R_F is selected as 100 kΩ.

Equation 5.

The primary goal of the acquisition system depicted in Figure 43 is to measure up to 20 harmonics in a 60-Hz power network. Thus, the analog front-end must have sufficient bandwidth to detect signals up to 1260 Hz, as shown in Equation 6.

Equation 6.

Based on the bandwidth found in Equation 6, the ADS8556 device is set to simultaneously sample all six channels at 15.36 kSPS, which provides enough samples to clearly resolve even the highest harmonic required.

The passband of the configuration shown in Figure 44 is determined by the –3-dB frequency according to Equation 7. The value of C_F is selected as 820 pF, which is a standard capacitance value available in 0603 size (surface-mount component) and such values, combined with that of R_F, result in sufficient bandwidth to accommodate the required 20 harmonics (at 60 Hz).

Equation 7.

The value of R₁ is selected as the parallel combination of R_IN and R_F to prevent the input bias current of the operational amplifier from generating an offset error.

The value of component C₁ is chosen as 0.1 µF to provide a low-impedance path for noise signals that can be picked up by R₁; this 0.1-µF capacitance value improves the EMI robustness and noise performance of the system.

The OPA2277 device is chosen for its low input offset voltage, low drift, bipolar swing, sufficient gain-bandwidth product and low quiescent current. For additional information on the procedure to select SAR ADC input drivers, see 16-bit 400KSPS 4-Ch. Multiplexed Data Acquisition Ref Design for High Voltage Inputs, Low Distortion, TIPD151.

The charge injection damping circuit is composed of R₂ (49.9 Ω) and C₂ (370 pF); these components reject high-frequency noise and meet the settling requirements of the ADS8556 device input.

Figure 45 shows the reference block used in this design.

Figure 45. Reference Block

For more information on the design of charge injection damping circuits and reference driving circuits for SAR ADCs, consult the reference guide Power-optimized 16-bit 1MSPS Data Acquisition Block for Lowest Distortion and Noise Reference Design, TIDU014.

8.2.3 Application Curve

Figure 46 shows the frequency spectrum of the data acquired by the ADS8556 device for a sinusoidal, 20-V_PP input at 60 Hz.

Figure 46. Frequency Spectrum for a Sinusoidal 20-V_PP Signal at 60 Hz

The ac performance parameters are:

• SNR: 91.9 dB
• THD: –99.68 dB
• SNDR: 91.23 dB
• SFDR: 103.65 dB