SBAS687B February   2015  – August 2015 AFE5818

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Digital Characteristics
    7. 8.7 Output Interface Timing
    8. 8.8 Serial Interface Timing Characteristics
    9. 8.9 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Low-Noise Amplifier
        1. 9.3.1.1 Input Signal Support
        2. 9.3.1.2 Input Circuit
        3. 9.3.1.3 LNA High-Pass Filter
        4. 9.3.1.4 LNA Input Impedance
        5. 9.3.1.5 LNA Gain Switch Response
        6. 9.3.1.6 LNA Noise Contribution
        7. 9.3.1.7 LNA Overload Recovery
      2. 9.3.2 Voltage-Controlled Attenuator
        1. 9.3.2.1 Digital TGC
        2. 9.3.2.2 Control Voltage Input
        3. 9.3.2.3 Voltage Attenuator Noise
      3. 9.3.3 Programmable Gain Amplifier (PGA)
        1. 9.3.3.1 PGA Clamp
        2. 9.3.3.2 Low-Pass Filter (LPF)
        3. 9.3.3.3 High-Pass Filter (HPF)
        4. 9.3.3.4 Noise
      4. 9.3.4 Analog-to-Digital Converter (ADC)
        1. 9.3.4.1 System Clock Input
        2. 9.3.4.2 System Clock Configuration for Multiple Devices
        3. 9.3.4.3 LVDS Interface
          1. 9.3.4.3.1 LVDS Buffer
          2. 9.3.4.3.2 LVDS Data Rate Modes
            1. 9.3.4.3.2.1 1X Data Rate Mode
            2. 9.3.4.3.2.2 2X Data Rate Mode
        4. 9.3.4.4 ADC Register, Digital Processing Description
          1. 9.3.4.4.1 Digital Offset
            1. 9.3.4.4.1.1 Manual Offset Correction
            2. 9.3.4.4.1.2 Auto Offset Correction Mode (Offset Correction using a Built-In Offset Calculation Function)
          2. 9.3.4.4.2 Digital Average
          3. 9.3.4.4.3 Digital Gain
          4. 9.3.4.4.4 Digital HPF
      5. 9.3.5 LVDS Synchronization Operation
      6. 9.3.6 Continuous-Wave (CW) Beamformer
        1. 9.3.6.1 16 × ƒcw Mode
        2. 9.3.6.2 8 × ƒcw and 4 × ƒcw Modes
        3. 9.3.6.3 1 × ƒcw Mode
        4. 9.3.6.4 CW High-Pass Filter
        5. 9.3.6.5 CW Clock Selection
        6. 9.3.6.6 CW Supporting Circuits
        7. 9.3.6.7 Power Management
          1. 9.3.6.7.1 VCA
          2. 9.3.6.7.2 ADC
    4. 9.4 Device Functional Modes
      1. 9.4.1 ADC Test Pattern Mode
        1. 9.4.1.1 Test Patterns
          1. 9.4.1.1.1 LVDS Test Pattern Mode
      2. 9.4.2 Partial Power-Up and Power-Down Mode
      3. 9.4.3 Global Power-Down Mode
      4. 9.4.4 TGC Configuration
      5. 9.4.5 CW Configuration
      6. 9.4.6 TGC + CW Mode
    5. 9.5 Programming
      1. 9.5.1 Serial Peripheral Interface (SPI) Operation
        1. 9.5.1.1 Register Readout
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
    3. 10.3 Do's and Don'ts
    4. 10.4 Initialization Set Up
  11. 11Power Supply Recommendations
    1. 11.1 Power Sequencing and Initialization
      1. 11.1.1 Power Sequencing
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Power Supply, Grounding, and Bypassing
      2. 12.1.2 Board Layout
    2. 12.2 Layout Example
  13. 13Register Maps
    1. 13.1 Serial Register Map
      1. 13.1.1 Global Register Map
        1. 13.1.1.1 Description of Global Register
          1. 13.1.1.1.1 Register 0 (address = 0h)
      2. 13.1.2 ADC Register Map
        1. 13.1.2.1 Description of ADC Registers
          1. 13.1.2.1.1  Register 1 (address = 1h)
          2. 13.1.2.1.2  Register 2 (address = 2h)
          3. 13.1.2.1.3  Register 3 (address = 3h)
          4. 13.1.2.1.4  Register 4 (address = 4h)
          5. 13.1.2.1.5  Register 5 (address = 5h)
          6. 13.1.2.1.6  Register 7 (address = 7h)
          7. 13.1.2.1.7  Register 8 (address = 8h)
          8. 13.1.2.1.8  Register 11 (address = Bh)
          9. 13.1.2.1.9  Register 13 (address = Dh)
          10. 13.1.2.1.10 Register 14 (address = Eh)
          11. 13.1.2.1.11 Register 15 (address = Fh)
          12. 13.1.2.1.12 Register 16 (address = 10h)
          13. 13.1.2.1.13 Register 17 (address = 11h)
          14. 13.1.2.1.14 Register 18 (address = 12h)
          15. 13.1.2.1.15 Register 19 (address = 13h)
          16. 13.1.2.1.16 Register 20 (address = 14h)
          17. 13.1.2.1.17 Register 21 (address = 15h)
          18. 13.1.2.1.18 Register 23 (address = 17h)
          19. 13.1.2.1.19 Register 24 (address = 18h)
          20. 13.1.2.1.20 Register 25 (address = 19h)
          21. 13.1.2.1.21 Register 26 (address = 1Ah)
          22. 13.1.2.1.22 Register 27 (address = 1Bh)
          23. 13.1.2.1.23 Register 28 (address = 1Ch)
          24. 13.1.2.1.24 Register 29 (address = 1Dh)
          25. 13.1.2.1.25 Register 30 (address = 1Eh)
          26. 13.1.2.1.26 Register 31 (address = 1Fh)
          27. 13.1.2.1.27 Register 32 (address = 20h)
          28. 13.1.2.1.28 Register 33 (address = 21h)
          29. 13.1.2.1.29 Register 35 (address = 23h)
          30. 13.1.2.1.30 Register 36 (address = 24h)
          31. 13.1.2.1.31 Register 37 (address = 25h)
          32. 13.1.2.1.32 Register 38 (address = 26h)
          33. 13.1.2.1.33 Register 39 (address = 27h)
          34. 13.1.2.1.34 Register 40 (address = 28h)
          35. 13.1.2.1.35 Register 41 (address = 29h)
          36. 13.1.2.1.36 Register 42 (address = 2Ah)
          37. 13.1.2.1.37 Register 43 (address = 2Bh)
          38. 13.1.2.1.38 Register 44 (address = 2Ch)
          39. 13.1.2.1.39 Register 45 (address = 2Dh)
          40. 13.1.2.1.40 Register 47 (address = 2Fh)
          41. 13.1.2.1.41 Register 48 (address = 30h)
          42. 13.1.2.1.42 Register 49 (address = 31h)
          43. 13.1.2.1.43 Register 50 (address = 32h)
          44. 13.1.2.1.44 Register 51 (address = 33h)
          45. 13.1.2.1.45 Register 52 (address = 34h)
          46. 13.1.2.1.46 Register 53 (address = 35h)
          47. 13.1.2.1.47 Register 54 (address = 36h)
          48. 13.1.2.1.48 Register 55 (address = 37h)
          49. 13.1.2.1.49 Register 56 (address = 38h)
          50. 13.1.2.1.50 Register 57 (address = 39h)
          51. 13.1.2.1.51 Register 59 (address = 3Bh)
          52. 13.1.2.1.52 Register 60 (address = 3Ch)
          53. 13.1.2.1.53 Register 67 (address = 43h)
      3. 13.1.3 VCA Register Map
        1. 13.1.3.1 Description of VCA Registers
          1. 13.1.3.1.1  Register 195 (address = C3h)
          2. 13.1.3.1.2  Register 196 (address = C4h)
          3. 13.1.3.1.3  Register 197 (address = C5h)
          4. 13.1.3.1.4  Register 198 (address = C6h)
          5. 13.1.3.1.5  Register 199 (address = C7h)
          6. 13.1.3.1.6  Register 200 (address = C8h)
          7. 13.1.3.1.7  Register 201 (address = C9h)
          8. 13.1.3.1.8  Register 203 (address = CBh)
          9. 13.1.3.1.9  Register 205 (address = CDh)
          10. 13.1.3.1.10 Register 213 (address = D5h)
          11. 13.1.3.1.11 Register 215 (address = D7h)
          12. 13.1.3.1.12 Register 216 (address = D8h)
          13. 13.1.3.1.13 Register 217 (address = D9h)
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Trademarks
    3. 14.3 Electrostatic Discharge Caution
    4. 14.4 Export Control Notice
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Tray Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • 16-Channel, Complete Analog Front-End:
    • LNA, VCAT, PGA, LPF, ADC, and CW Mixer
  • LNA with Programmable Gain:
    • Gain: 24 dB, 18 dB, and 12 dB
    • Linear Input Range:
      0.25 VPP, 0.5 VPP, and 1 VPP
    • Input-Referred Noise:
      0.63 nV/√Hz, 0.7 nV/√Hz, and 0.9 nV/√Hz
    • Programmable Active Termination
  • Voltage-Controlled Attenuator (VCAT): 40 dB
  • Programmable Gain Amplifier (PGA):
    24 dB and 30 dB
  • Total Signal Chain Gain: 54 dB (max)
  • 3rd-Order, Linear-Phase LPF:
    • 10 MHz, 15 MHz, 20 MHz, 30 MHz, 35 MHz, and 50 MHz
  • Analog-to-Digital Converter (ADC):
    • 14-Bit ADC: 75-dBFS SNR at 65 MSPS
    • 12-Bit ADC: 72-dBFS SNR at 80 MSPS
  • LVDS Interface Maximum Speed of 1 Gbps
  • Noise and Power Optimizations (Full-Channel):
    • 140 mW/Ch at 0.75 nV/√Hz, 65 MSPS
    • 91.5 mW/Ch at 1.1 nV/√Hz, 40 MSPS
    • 80 mW/Ch at CW Mode
  • Excellent Device-to-Device Gain Matching:
    • ±0.5 dB (typical) and ±1.1 dB (max)
  • Low Harmonic Distortion
  • Fast and Consistent Overload Recovery
  • Passive Mixer for CWD:
    • Low Close-In Phase Noise:
      –156 dBc/Hz at 1 kHz Off 2.5-MHz Carrier
    • Phase Resolution: λ / 16
    • Supports 16X, 8X, 4X, and 1X CW Clocks
    • 12-dB Suppression on 3rd and 5th Harmonics
    • CWD High-Pass Filter Rejects Undesired Low-Frequency Signals < 1 kHz
  • Small Package: 15-mm × 15-mm NFBGA-289

2 Applications

  • Medical Ultrasound Imaging
  • Nondestructive Evaluation Equipment
  • Sonar Imaging Equipment
  • Multichannel, High-Speed Data Acquisition

3 Description

The AFE5818 is a highly-integrated, analog front-end (AFE) solution specifically designed for ultrasound systems where high performance and small size are required. The device integrates a complete time-gain-control (TGC) imaging path and a continuous wave Doppler (CWD) path. The device also allows various power and noise combinations to be selected to optimize system performance. Therefore, the AFE5818 is a suitable ultrasound AFE solution for high-end and portable systems

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
AFE5818 NFBGA (289) 15.00 mm × 15.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Block Diagram

AFE5818 simp_fbd_sbas624.gif