SLUS920A July   2009  – July 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Battery Voltage Regulation
      2. 8.3.2  Battery Current Regulation
      3. 8.3.3  Input Adapter Current Regulation
      4. 8.3.4  Adapter Detect and Power Up
      5. 8.3.5  Enable and Disable Charging
      6. 8.3.6  System Power Selector
      7. 8.3.7  Battery Learn Cycles
      8. 8.3.8  Automatic Internal Soft-Start Charger Current
      9. 8.3.9  Converter Operation
      10. 8.3.10 Synchronous and Non-Synchronous Operation
      11. 8.3.11 High Accuracy IADAPT Using Current Sense Amplifier (CSA)
      12. 8.3.12 Input Overvoltage Protection (ACOV)
      13. 8.3.13 Input Undervoltage Lockout (UVLO)
      14. 8.3.14 AC Lowvoltage (ACLOWV)
      15. 8.3.15 Battery Overvoltage Protection
      16. 8.3.16 Battery Shorted (Battery Undervoltage) Protection
      17. 8.3.17 Charge Overcurrent Protection
      18. 8.3.18 Thermal Shutdown Protection
      19. 8.3.19 Adapter Detected Status Register (ACGOOD Pin)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Input Overpower Protection (ACOP)
        1. 8.4.1.1 Conditions For ACOP Latch Off
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Capacitance Calculation
        2. 9.2.2.2 Inductor Selection
        3. 9.2.2.3 Input Capacitor
        4. 9.2.2.4 Output Capacitor
        5. 9.2.2.5 Power MOSFET Selection
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RHD Package
28-Pin VQFN
Top View
bq24753A po_lus920.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
ACDET 5 I Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider from adapter input to ACDET pin to AGND pin. Adapter voltage is detected if ACDET-pin voltage is greater than 2.4 V. The IADAPT current sense amplifier is active when the ACDET pin voltage is greater than 0.6 V.
ACDRV 4 O AC adapter to system-switch driver output. Connect directly to the gate of the ACFET P-channel power MOSFET and the reverse conduction blocking P-channel power MOSFET. Connect both FETs as common-source. Connect the ACFET drain to the system-load side. The PVCC should be connected to the common-source node to ensure that the driver logic is always active when needed. If needed, an optional capacitor from gate to source of the ACFET is used to slow down the ON and OFF times. The internal gate drive is asymmetrical, allowing a quick turn-off and slower turn-on in addition to the internal break-before-make logic with respect to the BATDRV. The output goes into linear regulation mode when the input sensed current exceeds the ACOC threshold. ACDRV is latched off after ACOP voltage exceeds 2 V, to protect the charging system from an ACFET-overpower condition.
ACGOOD 13 O Valid adapter active-low detect logic open-drain output. Pulled low when Input voltage is above programmed ACDET. Connect a 10-kΩ pullup resistor from ACGOOD to VREF, or to a different pullup-supply rail.
ACN 2 I Adapter current sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from ACN pin to AGND for common-mode filtering.
ACOP 7 I Input power limit set input. Program the input overpower time constant by placing a ceramic capacitor from ACOP to AGND. The capacitor sets the time that the input current limit, ACOC, can be sustained before exceeding the power-MOSFET power limit. When the ACOP voltage exceeds 2 V, then the ACDRV latches off to protect the charge system from an overpower condition, ACOP. Reset latch by toggling ACDET or PVCC_UVLO.
ACP 3 I Adapter current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from ACP pin to AGND for common-mode filtering.
ACSET 6 I Adapter current set input. The voltage ratio of ACSET voltage versus VDAC voltage programs the input current regulation set-point during Dynamic Power Management (DPM). Program by connecting a resistor divider from VDAC to ACSET to AGND; or by connecting the output of an external DAC to the ACSET pin and connect the DAC supply to the VDAC pin.
AGND 9 – Analog ground. Ground connection for low-current sensitive analog and digital signals. On PCB layout, connect to the analog ground plane, and only connect to PGND through the thermal pad underneath the IC.
BAT 17 – Battery voltage remote sense. Directly connect a kelvin sense trace from the battery pack positive terminal to the BAT pin to accurately sense the battery pack voltage. Place a 0.1-μF capacitor from BAT to AGND close to the IC to filter high-frequency noise.
BATDRV 14 O Battery to system switch driver output. Gate drive for the battery to system load BAT PMOS power FET to isolate the system from the battery to prevent current flow from the system to the battery, while allowing a low impedance path from battery to system and while discharging the battery pack to the system load. Connect this pin directly to the gate of the input BAT P-channel power MOSFET. Connect the source of the FET to the system load voltage node. Connect the drain of the FET to the battery pack positive node. An optional capacitor is placed from the gate to the source to slow down the switching times. The internal gate drive is asymmetrical to allow a quick turn-off and slower turn-on, in addition to the internal break-before-make logic with respect to ACDRV.
BTST 27 – PWM high side driver positive supply. Connect a 0.1-μF bootstrap ceramic capacitor from BTST to PH. Connect a small bootstrap Schottky diode from REGN to BTST.
CELLS 20 I 2, 3 or 4 cells selection logic input. Logic low programs 3 cell. Logic high programs 4 cell. Floating programs 2 cell.
CHGEN 1 I Charge enable active-low logic input. LO enables charge. HI disables charge.
HIDRV 26 O PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace.
IADAPT 15 O Adapter current sense amplifier output. IADAPT voltage is 20 times the differential voltage across ACP-ACN. Place a 100-pF or less ceramic decoupling capacitor from IADAPT to AGND.
LEARN 21 I Learn mode logic input control pin — logic high to override system selector when adapter is present, the battery is discharged to recalibrate the battery-pack gas gauge. When adapter is present and LEARN is high, battery charging is disabled, the adapter is disconnected (ACDRV is off), and the battery is connected to system (BATDRV is on). System selector automatically switches to adapter if battery is discharged below LOWBAT (3 V). When adapter is present and LEARN is low, the adapter is connected to system in normal selector logic (ACDRV is on and BATDRV is off), allowing battery charging. If adapter is not present, the battery is always connected to the system (ACDRV is off and BATDRV is on).
LODRV 23 O PWM low side driver output. Connect to the gate of the low-side power MOSFET with a short trace.
OVPSET 8 – Set input over voltage protection threshold. Charge is disabled and ACDRV is turned off if adapter input voltage is higher than the OVPSET programmed threshold. Input overvoltage, ACOV, disables charge and ACDRV when OVPSET > 3.1 V. ACOV does not latch. Program the overvoltage protection threshold by connecting a resistor divider from adapter input to OVPSET pin to AGND pin.
PGND 22 – Power ground. Ground connection for high-current power converter node. On PCB layout, connect directly to source of low-side power MOSFET, to ground connection of in put and output capacitors of the charger. Only connect to AGND through the Thermal Pad underneath the IC.
PH 25 – PWM high side driver negative supply. Connect to the phase switching node (junction of the low-side power MOSFET drain, high-side power MOSFET source, and output inductor). Connect the 0.1-μF bootstrap capacitor from PH to BTST.
PVCC 28 – IC power positive supply. Connect to the common-source (diode-OR) point: source of high-side P-channel MOSFET and source of reverse-blocking power P-channel MOSFET. Place a 0.1-μF ceramic capacitor from PVCC to PGND pin close to the IC.
REGN 24 O PWM low side driver positive 6-V supply output. Connect a 1-μF ceramic capacitor from REGN to PGND, close to the IC. Use for high-side driver bootstrap voltage by connecting a small-signal Schottky diode from REGN to BTST. REGN is disabled when CHGEN is high.
SRN 18 I Charge current sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from SRN pin to AGND for common-mode filtering.
SRP 19 I Charge current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from SRP pin to AGND for common-mode filtering.
SRSET 16 I Charge current set input. The voltage ratio of SRSET voltage versus VDAC voltage programs the charge current regulation set-point. Program by connecting a resistor divider from VDAC to SRSET to AGND; or by connecting the output of an external DAC to SRSET pin and connect the DAC supply to VDAC pin.
VADJ 12 I Charge voltage set input. The voltage ratio of VADJ voltage versus VDAC voltage programs the battery voltage regulation set-point. Program by connecting a resistor divider from VDAC to VADJ, to AGND; or, by connecting the output of an external DAC to VADJ, and connect the DAC supply to VDAC. VADJ connected to REGN programs the default of 4.2 V per cell.
VDAC 11 I Charge voltage set reference input. Connect the VREF or external DAC voltage source to the VDAC pin. Battery voltage, charge current, and input current are programmed as a ratio of the VDAC pin voltage versus the VADJ, SRSET, and ACSET pin voltages, respectively. Place resistor dividers from VDAC to VADJ, SRSET, and ACSET pins to AGND for programming. A DAC could be used by connecting the DAC supply to VDAC and connecting the output to VADJ, SRSET, or ACSET.
VREF 10 O 3.3-V regulated voltage output. Place a 1-μF ceramic capacitor from VREF to AGND pin close to the IC. This voltage could be used for ratiometric programming of voltage and current regulation. Do not apply an external voltage source on this pin.
Thermal Pad Exposed pad beneath the IC. AGND and PGND star-connected only at the Thermal Pad plane. Always solder Thermal Pad to the board, and have vias on the Thermal Pad plane connecting to AGND and PGND planes. It also serves as a thermal pad to dissipate the heat.