SLUS920A Data sheet

7 Specifications

7.1 Absolute Maximum Ratings

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Electrical Characteristics

7.6 Timing Requirements

7.7 Typical Characteristics

Table 1. Table of Graphs⁽¹⁾

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メカニカル・データ（パッケージ｜ピン）

サーマルパッド・メカニカル・データ

発注情報

SLUS920A July 2009 – July 2015

PRODUCTION DATA.

RHD|28
- MPQF133F

RHD|28
- QFND050K

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
Voltage range	PVCC, ACP, ACN, SRP, SRN, BAT, BATDRV, ACDRV	–0.3	30	V
	PH	–1	30
	REGN, LODRV, VREF, VDAC, VADJ, ACSET, SRSET, ACDET, ACOP, CHGEN, CELLS, STAT, ACGOOD, LEARN, OVPSET	–0.3	7
	VREF, IADAPT	–0.3	3.6
	BTST, HIDRV with respect to AGND and PGND	–0.3	36
Maximum difference voltage	ACP–ACN, SRP–SRN, AGND–PGND	–0.5	0.5	V
Junction temperature, T_J		–40	155	°C
Storage temperature, T_stg		–55	155	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the data book for thermal limitations and considerations of packages.

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Voltage range	PH	–1	24	V
	PVCC, ACP, ACN, SRP, SRN, BAT, BATDRV, ACDRV	0	24	V
	REGN, LODRV, VADJ	0	6.5	V
	VDAC, IADAPT	0	3.6	V
	VREF	0	3.3	V
	ACSET, SRSET, TS, ACDET, ACOP, CHGEN, CELLS, ACGOOD, LEARN, OVPSET	0	5.5	V
	BTST, HIDRV with respect to AGND and PGND	0	30	V
	AGND, PGND	–0.3	0.3	V
Maximum difference voltage	ACP–ACN, SRP–SRN	–0.3	0.3	V
Junction temperature range, T_J		–40	125	°C
Storage temperature range, T_stg		–55	150	°C

THERMAL METRIC⁽¹⁾		bq24753A	UNIT
		RHD (VQFN)
		28 PINS
R_θJA	Junction-to-ambient thermal resistance	39	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7 V ≤ V_PVCC ≤ 24 V, 0°C < T_J < 125°C, typical values are at T_A = 25°C, with respect to AGND (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
OPERATING CONDITIONS
V_{PVCC_OP}	PVCC Input voltage operating range		8		24	V
CHARGE VOLTAGE REGULATION
V_{BAT_REG_RNG}	BAT voltage regulation range	4-4.512 V per cell, times 2,3,4 cells	8		18.048	V
V_{VDAC_OP}	VDAC reference voltage range		2.6		3.6	V
V_{ADJ_OP}	VADJ voltage range		0		REGN	V
	Charge voltage regulation accuracy	8 V, 8.4 V, 9.024 V	–0.5%		0.5%
		12 V, 12.6 V, 13.536 V	–0.5%		0.5%
		16 V, 16.8 V, 18.048 V	–0.5%		0.5%
	Charge voltage regulation set to default to 4.2 V per cell	VADJ connected to REGN, 8.4 V, 12.6 V, 16.8 V	–0.5%		0.5%
CHARGE CURRENT REGULATION
V_{IREG_CHG}	Charge current regulation differential voltage range	V_{IREG_CHG} = V_SRP – V_SRN	0		100	mV
V_{SRSET_OP}	SRSET voltage range		0		VDAC	V
	Charge current regulation accuracy	V_{IREG_CHG} = 40–100 mV	–3%		3%
		V_{IREG_CHG} = 20 mV	–5%		5%
		V_{IREG_CHG} = 5 mV	–25%		25%
		V_{IREG_CHG} = 1.5 mV (V_BAT>4V)	–33%		33%
INPUT CURRENT REGULATION
V_{IREG_DPM}	Adapter current regulation differential voltage range	V_{IREG_DPM} = V_ACP – V_ACN	0		100	mV
V_{ACSET_OP}	ACSET voltage range		0		VDAC	V
	Input current regulation accuracy	V_{IREG_DPM} = 40–100 mV	–3%		3%
		V_{IREG_DPM} = 20 mV	–5%		5%
		V_{IREG_DPM} = 5 mV	–25%		25%
		V_{IREG_DPM} = 1.5 mV	–33%		33%
VREF REGULATOR
V_{VREF_REG}	VREF regulator voltage	V_ACDET > 0.6 V, 0-30 mA	3.267	3.3	3.333	V
I_{VREF_LIM}	VREF current limit	V_VREF = 0 V, V_ACDET > 0.6 V	35		80	mA
REGN REGULATOR
V_{REGN_REG}	REGN regulator voltage	V_ACDET > 0.6 V, 0-75 mA, PVCC > 10 V	5.6	5.9	6.2	V
I_{REGN_LIM}	REGN current limit	V_REGN = 0 V, V_ACDET > 0.6 V	90		135	mA
ADAPTER CURRENT SENSE AMPLIFIER
V_{ACP/N_OP}	Input common mode range	Voltage on ACP/ACN	0		24	V
V_IADAPT	IADAPT output voltage range		0		2	V
I_IADAPT	IADAPT output current		0		1	mA
A_IADAPT	Current sense amplifier voltage gain	A_IADAPT = V_IADAPT / V_{IREG_DPM}		20		V/V
	Adapter current sense accuracy	V_{IREG_DPM} = 40–100 mV	–2%		2%
		V_{IREG_DPM} = 20 mV	–3%		3%
		V_{IREG_DPM} = 5 mV	–25%		25%
		V_{IREG_DPM} = 1.5 mV	–33%		33%
I_{IADAPT_LIM}	Output current limit	V_IADAPT = 0 V	1			mA
C_{IADAPT_MAX}	Maximum output load capacitance	For stability with 0 mA to 1 mA load			100	pF
ACDET COMPARATOR
V_{ACDET_CHG}	ACDET adapter-detect rising threshold	Min voltage to enable charging, V_ACDET rising	2.376	2.40	2.424	V
V_{ACDET_CHG_HYS}	ACDET falling hysteresis	V_ACDET falling		40		mV
	deglitch time after V_ACDET rising	V_ACDET rising above 2.4V	518	700	908	ms
	deglitch time after V_ACDET falling	V_ACDET falling below 2.4V	7	9	11	ms
V_{ACDET_BIAS}	ACDET enable-bias rising threshold	Min voltage to enable all bias, V_ACDET rising	0.56	0.62	0.68	V
V_{ACDET_BIAS_HYS}	Adapter present falling hysteresis	V_ACDET falling		20		mV
	ACDET_BIAS rising deglitch	V_ACDET rising above 0.62V		10		μs
	ACDET_BIAS falling deglitch	V_ACDET falling below 0.62V		10		μs
PVCC / BAT COMPARATOR
V_{PVCC-BAT_OP}	Differential Voltage from PVCC to BAT		–20		24	V
V_{PVCC-BAT_FALL}	PVCC to BAT falling threshold	V_PVCC – V_BAT to turn off ACFET	140	185	240	mV
V_{PVCC-BAT__HYS}	PVCC to BAT hysteresis			50		mV
	PVCC to BAT Rising Deglitch	V_PVCC – V_BAT > V_{PVCC-BAT_RISE}	7	9	11	ms
	PVCC to BAT Falling Deglitch	V_PVCC – V_BAT < V_{PVCC-BAT_FALL}		6		μs
OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS (ACGOOD)
V_{OUT_LO}	Output low saturation voltage	Sink Current = 5 mA			0.5	V
	Delay between system power selector (ACDRV and BATDRV) switching and ACGOOD edge			10		μs
INPUT UNDERVOLTAGE LOCK-OUT COMPARATOR (UVLO)
UVLO	AC Undervoltage rising threshold to exit UVLO	Measured on PVCC	3.5	4	4.5	V
UVLO_(HYS)	AC Undervoltage hysteresis, falling			260		mV
AC LOWVOLTAGE COMPARATOR (ACLOWV)
V_ACLOWV	AC low voltage rising threshold	Measure on ACP pin		3.6		V
V_ACLOWV	AC low voltage falling threshold	Measure on ACP pin		3		V
ACN / BAT COMPARATOR
V_{ACN-BAT_FALL}	ACN to BAT falling threshold	V_ACN – V_BAT to turn on BATDRV	175	285	340	mV
V_{ACN-BAT_HYS}	ACN to BAT hysteresis			50		mV
	ACN to BAT rising deglitch	V_ACN – V_BAT > V_{ACN-BAT_RISE}		20		μs
	ACN to BAT falling deglitch	V_ACN – V_BAT < V_{ACN-BAT_FALL}		6		μs
BAT OVERVOLTAGE COMPARATOR
V_{OV_RISE}	Overvoltage rising threshold	As percentage of V_{BAT_REG}		104%
V_{OV_FALL}	Overvoltage falling threshold	As percentage of V_{BAT_REG}		102%
BAT SHORT (UNDERVOLTAGE) COMPARATOR
V_{BAT_SHORT_FALL}	V_BAT falling threshold to begin C/8 charge	V_BAT falling	2.75	2.9	3.05	V/cell
V_{BAT_SHORT_HYS}	BATSHORT hysteresis	V_BAT rising	230	250	270	mV/cell
	Deglitch time of V_BAT rising to resume full charge	V_BAT > V_{BAT_SHORT}+V_{BAT_SHORT_HYS}		1.5		s
	Deglitch time of V_BAT falling to begin C/8 charge	V_BAT < V_{BAT_SHORT}		1.5		s
	BATSHORT EXIT delay to turn on BATFET and turn off ACFET when LEARN=HIGH			600		ms
	BATSHORT ENTRY delay to turn off BATFET and turn on ACFET when LEARN=HIGH			10		μs
CHARGE OVERCURRENT COMPARATOR
V_OC	Charge overcurrent rising threshold	As percentage of I_{REG_CHG}		145%
OCP Floor	Minimum overcurrent current limit	Measure at (SRP-SRN)		50		mV
CHARGE UNDERCURRENT COMPARATOR (SYNCHRONOUS TO NON-SYNCHRONOUS TRANSITION)
V_{ISYNSET_FALL}	Charge undercurrent falling threshold	Changing from synchronous to non-synchronous	9.75	13	16.25	mV
V_{ISYNSET_HYS}	Charge undercurrent rising hysteresis			8		mV
	Charge undercurrent, falling-current deglitch	V_{IREG_DPM} < V_ISYNSET		20		μs
	Charge undercurrent, rising-current deglitch	V_{IREG_DPM} < V_ISYNSET		640		μs
INPUT OVERPOWER COMPARATOR (ACOP)
V_ACOC	ACOC Gain for initial ACOC current limit (Percentage of programmed VIREG_DPM)	Begins 700 ms after ACDET, V_ACSET=1V Input current limited to this threshold for fault protection	250	265	283	% V_{IREG_DPM}
V_{ACOC_CEILING}	Maximum ACOC input current limit (V_ACP–V_ACN)max	Internally limited ceiling, V_{ACOC_MAX} = (V_ACP–V_ACN)max		100		mV
	ACOP Latch Blankout Time with ACOC active (begins 700 ms after ACDET)	Begins 700 ms after ACDET (does not allow ACOP latch-off, and no ACOP source current)		2		ms
V_ACOP	ACOP pin latch-off threshold voltage (See ACOP in Pin Configuration and Functions)		1.95	2	2.05	V
K_ACOP	Gain for ACOP Source Current when in ACOC	Current source on when in ACOC limit. Function of voltage across power FET I_{ACOP_SOURCE} = K_ACOP ×(V_PVCC -V_ACP)		18		μA / V
I_{ACOP_SINK}	ACOP Sink Current when not in ACOC ACOP Latch is reset by going below ACDET or UVLO	Current sink on when not in ACOC		5		μA
V_ACN-SHORT	ACN Short protection threshold latching	ACN < 2.4 V, ACDET > 2.4 V		2.4		V
INPUT OVERVOLTAGE COMPARATOR (ACOV)
V_ACOV	AC Overvoltage rising threshold on OVPSET (See OVPSET in Pin Configuration and Functions)	Measured on OVPSET	3.007	3.1	3.193	V
V_{ACOV_HYS}	AC Overvoltage rising deglitch			1.3		ms
V_{ACOV_HYS}	AC Overvoltage falling deglitch			1.3		ms
THERMAL SHUTDOWN COMPARATOR
T_SHUT	Thermal shutdown rising temperature	Temperature Increasing		155		°C
T_{SHUT_HYS}	Thermal shutdown hysteresis, falling			20		°C
BATTERY SWITCH (BATDRV) DRIVER
R_{DS(off)_BAT}	BATFET Turn-off resistance	V_ACN > 5 V			160	Ω
R_{DS(on)_BAT}	BATFET Turn-on resistance	V_ACN > 5 V			3	kΩ
V_{BATDRV_REG}	BATFET drive voltage	V_{BATDRV_REG} = V_ACN – V_BATDRV when V_ACN > 5 V and BATFET is on		6.5		V
	BATFET Power-up delay	Delay to turn off BATFET after adapter is detected (after V_ACDET > 2.4 V)	518	700	908	ms
AC SWITCH (ACDRV) DRIVER
R_{DS(off)_AC}	ACFET turn-off resistance	V_PVCC > 5 V			80	Ω
R_{DS(on)_AC}	ACFET turn-on resistance	V_PVCC > 5 V			2.5	kΩ
V_{ACDRV_REG}	ACFET drive voltage	V_{ACDRV_REG} = V_PVCC – V_ACDRV when V_PVCC > 5 V and ACFET is on		6.5		V
	ACFET Power-up Delay	Delay to turn on ACFET after adapter is detected (after V_ACDET > 2.4 V)	518	700	908	ms
PWM HIGH SIDE DRIVER (HIDRV)
R_{DS(on)_HI}	High side driver turn-on resistance	V_BTST – V_PH = 5.5 V, tested at 100 mA		3	6	Ω
R_{DS(off)_HI}	High side driver turn-off resistance	V_BTST – V_PH = 5.5 V, tested at 100 mA		0.7	1.4	Ω
V_{BTST_REFRESH}	Bootstrap refresh comparator threshold voltage	V_BTST – V_PH when low side refresh pulse is requested	4			V
PWM LOW SIDE DRIVER (LODRV)
R_{DS(on)_LO}	Low side driver turn-on resistance	REGN = 6 V, tested at 100 mA		3	6	Ω
R_{DS(off)_LO}	Low side driver turn-off resistance	REGN = 6 V, tested at 100 mA		0.6	1.2	Ω
PWM OSCILLATOR
F_SW	PWM switching frequency		240	300	360	kHz
V_{RAMP_HEIGHT}	PWM ramp height	As percentage of PVCC		6.6		%PVCC
QUIESCENT CURRENT
I_{OFF_STATE}	Total off-state quiescent current into pins SRP, SRN, BAT, BTST, PH, PVCC, ACP, ACN	V_BAT = 16.8 V, V_ACDET < 0.6 V, V_PVCC > 5 V, T_J = 0 to 85°C		7	10	μA
I_{BATQ_CD}	Total quiescent current into pins: SRP, SRN, BAT, BTST, PH	Adapter present, V_ACDET > 2.4 V, charge disabled		100	200	μA
I_AC	Adapter quiescent current	V_PVCC = 20 V, charge disabled		1	1.5	mA
INTERNAL SOFT START (8 steps to regulation current)
	Soft start steps			8		step
	Soft start step time			1.7		ms
CHARGER SECTION POWER-UP SEQUENCING
	Charge-enable delay after power-up	Delay from when adapter is detected to when the charger is allowed to turn on	518	700	908	ms
LOGIC INPUT PIN CHARACTERISTICS (CHGEN, LEARN)
V_{IN_LO}	Input low threshold voltage				0.8	V
V_{IN_HI}	Input high threshold voltage		2.1			V
I_BIAS	Input bias current	V_CHGEN = 0 to V_REGN			1	μA
t_{CHGEN_DEGLITCH}	Charge enable deglitch time	ACDET > 2.4 V, CHGEN rising		2		ms
LOGIC INPUT PIN CHARACTERISTICS (CELLS)
V_{IN_LO}	Input low threshold voltage, 3 cells	CELLS voltage falling edge			0.5	V
V_{IN_MID}	Input mid threshold voltage, 2 cells	CELLS voltage rising for MIN, CELLS voltage falling for MAX	0.8		1.8
V_{IN_HI}	Input high threshold voltage, 4 cells	CELLS voltage rising	2.5
I_{BIAS_FLOAT}	Input bias float current for 2-cell selection	V_CHGEN = 0 to V_REGN	–1		1	μA

7 V ≤ V_PVCC ≤ 24 V, 0°C < T_J < 125°C, typical values are at T_A = 25°C, with respect to AGND (unless otherwise noted)

AC / BAT MOSFET DRIVERS TIMING

Driver dead time – Dead time when switching between ACDRV and BATDRV

PWM DRIVERS TIMING

Driver Dead Time – Dead time when switching between LODRV and HIDRV. No load at LODRV and HIDRV

		FIGURE
VREF Load and Line Regulation	vs Load Current	Figure 1
REGN Load and Line Regulation	vs Load Current	Figure 2
BAT Voltage	vs VADJ/VDAC Ratio	Figure 3
Charge Current	vs SRSET/VDAC Ratio	Figure 4
Input Current	vs ACSET/VDAC Ratio	Figure 5
BAT Voltage Regulation Accuracy	vs Charge Current	Figure 6
BAT Voltage Regulation Accuracy		Figure 7
Charge Current Regulation Accuracy		Figure 8
Input Current Regulation (DPM) Accuracy		Figure 9
V_IADAPT Input Current Sense Amplifier Accuracy		Figure 10
Input Regulation Current (DPM), and Charge Current	vs System Current	Figure 11
Transient System Load (DPM) Response		Figure 12
Fast (DPM) Response		Figure 13
Charge Current Regulation	vs BAT Voltage	Figure 14
Efficiency	vs Battery Charge Current	Figure 15
Battery Removal (from Constant Current Mode)		Figure 16
ACDRV and BATDRV Startup		Figure 17
REF and REGN Startup		Figure 18
System Selector on Adapter Insertion with 390-μF SYS-to-PGND System Capacitor		Figure 19
System Selector on Adapter Removal with 390-μF SYS-to-PGND System Capacitor		Figure 20
System Selector LEARN Turn-On with 390-μF SYS-to-PGND System Capacitor		Figure 21
System Selector LEARN Turn-Off with 390-μF SYS-to-PGND System Capacitor		Figure 22
System Selector on Adapter Insertion		Figure 23
Selector Gate Drive Voltages, 700 ms delay after ACDET		Figure 24
System Selector when Adapter Removed		Figure 25
Charge Enable / Disable and Current Soft-Start		Figure 26
Nonsynchronous to Synchronous Transition		Figure 27
Synchronous to Nonsynchronous Transition		Figure 28
Near 100% Duty Cycle Bootstrap Recharge Pulse		Figure 29
Battery Shorted Charger Response, Over Current Protection (OCP) and Charge Current Regulation		Figure 30
Continuous Conduction Mode (CCM) Switching Waveforms		Figure 32
Discontinuous Conduction Mode (DCM) Switching Waveforms		Figure 31
BATSHORT Entry		Figure 33
BATSHORT Exit		Figure 34

(1) Test results based on Figure 37 application schematic. V_IN = 20 V, V_BAT = 3-cell Li-Ion, I_CHG = 3 A, I_{ADAPTER_LIMIT} = 4 A, T_A = 25°C, unless otherwise specified.