SLUSC27C April   2015  – March 2017

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Power Up
        1. 7.3.1.1 Battery Only
        2. 7.3.1.2 Adapter Detect and ACOK Output
          1. 7.3.1.2.1 Adapter Overvoltage (ACOVP)
      2. 7.3.2 System Power Selection
      3. 7.3.3 Enable and Disable Charging
        1. 7.3.3.1 Automatic Internal Soft-Start Charger Current
      4. 7.3.4 Current and Power Monitor
        1. 7.3.4.1 High Accuracy Current Sense Amplifier (IADP and IDCHG)
        2. 7.3.4.2 High Accuracy Power Sense Amplifier (PMON)
      5. 7.3.5 Processor Hot Indication for CPU Throttling
      6. 7.3.6 Converter Operation
        1. 7.3.6.1 Continuous Conduction Mode (CCM)
        2. 7.3.6.2 Discontinuous Conduction Mode (DCM)
        3. 7.3.6.3 Non-Sync Mode and Light Load Comparator
        4. 7.3.6.4 EMI Switching Frequency Adjust
      7. 7.3.7 Battery LEARN Cycle
      8. 7.3.8 Charger Timeout
      9. 7.3.9 Device Protections Features
        1. 7.3.9.1 Input Overcurrent Protection (ACOC)
        2. 7.3.9.2 Charge Overcurrent Protection (CHGOCP)
        3. 7.3.9.3 Battery Overvoltage Protection (BATOVP)
        4. 7.3.9.4 Battery Short
        5. 7.3.9.5 Thermal Shutdown Protection (TSHUT)
        6. 7.3.9.6 Inductor Short, MOSFET Short Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Battery Charging
      2. 7.4.2 Hybrid Power Boost Mode
        1. 7.4.2.1 Battery Discharge Current Regulation in Hybrid Power Boost Mode
    5. 7.5 Programming
      1. 7.5.1 SMBus Interface
        1. 7.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 7.5.1.2 Timing Diagrams
    6. 7.6 Register Maps
      1. 7.6.1  Battery-Charger Commands
      2. 7.6.2  Setting Charger Options
        1. 7.6.2.1 ChargeOption0 Register
      3. 7.6.3  ChargeOption1 Register
      4. 7.6.4  ChargeOption2 Register
      5. 7.6.5  ChargeOption3 Register
      6. 7.6.6  ProchotOption0 Register
      7. 7.6.7  ProchotOption1 Register
      8. 7.6.8  ProchotStatus Register
      9. 7.6.9  Setting the Charge Current
      10. 7.6.10 Setting the Charge Voltage
      11. 7.6.11 Setting Input Current
      12. 7.6.12 Setting the Discharge Current
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Negative Output Voltage Protection
        2. 8.2.2.2 Reverse Input Voltage Protection
        3. 8.2.2.3 Reduce Battery Quiescent Current
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Input Capacitor
        6. 8.2.2.6 Output Capacitor
        7. 8.2.2.7 Power MOSFETs Selection
        8. 8.2.2.8 Input Filter Design
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
      1. 10.2.1 Layout Consideration of Current Path
      2. 10.2.2 Layout Consideration of Short Circuit Protection
      3. 10.2.3 Layout Consideration for Short Circuit Protection
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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Detailed Description

Overview

The bq24780S is a 1-4 cell battery charge controller with power selection for space-constrained, multi-chemistry portable applications such as notebook and detachable ultrabook. It supports wide input range of input sources from 4.5 V to 24 V, and 1-4 cell battery for a versatile solution.

The bq24780S supports automatic system power source selection with separate drivers for n-channel MOSFETS on the adapter side and battery side.

The bq24780S features Dynamic Power Management (DPM) to limit the input power and avoid AC adapter over-loading. During battery charging, as the system power increases, the charging current will reduce to maintain total input current below adapter rating. If system power demand is temporarily exceeds adapter rating, the bq24780S supports hybrid power boost mode (previously called "turbo boost mode") to allow battery discharge energy to supplement system power. For details of hybrid power boost mode, refer to Device Functional Modes section.

The bq24780S closely monitors system power (PMON), input current (IADP) and battery discharge current (IDCHG) with highly accurate current sense amplifiers. If current is too high, adapter or battery is removed, a PROCHOT signal is asserted to CPU so that the CPU optimizes its performance to the power available to the system.

The SMBus controls input current, charge current and charge voltage registers with high resolution, high accuracy regulation limits. It also sets the PROCHOT timing and threshold profile to meet system requirements.

Functional Block Diagram

bq24780S fbd_slusc27.gif

Feature Description

Device Power Up

The bq24780S gets power from adapter or battery. After VCC is above its UVLO threshold, the device wakes up and starts communication.

Battery Only

When VCC voltage is above UVLO, bq24780S powers up to turn on BATFET and starts SMBus communication. By default, bq24780S stays in low power mode (REG0x12[15] = 1) with lowest quiescent current. When REG0x12[15] is set to 0, the device enters performance mode. User can enable IDCHG buffer, PMON, PROCHOT or comparator through SMBus. REGN LDO is enabled (except for IDCHG buffer) for accurate reference.

Adapter Detect and ACOK Output

An external resistor divider attenuates the adapter voltage before it goes to ACDET. The adapter detect threshold should typically be programmed to a value greater than the maximum battery voltage, but lower than the maximum allowed adapter voltage. When ACDET is above 0.6V, all bias circuits are enabled.

The open drain ACOK output can be pulled to external rail under the following conditions:

  • VVCC_UVLOZ < VVCC < ACOVP
  • VACDET > 2.4 V
  • VVCC – VSRN > VVCC_SRN_FALL + VVCC_SRN_HYST

The REG0x37[11] tracks the status of ACOK pin. ACOK deglitch time is 150ms at the first time adapter plug-in, and 1.3 sec at the following plug-ins after VCC or SRN is above its UVLOZ.

Adapter Overvoltage (ACOVP)

When the VCC pin voltage is higher than 26 V, it is considered adapter over voltage. ACOK is pulled low, and charge is disabled. ACFET/RBFET are turned off to disconnect the high voltage adapter to system during ACOVP. BATFET is turned on if turn-on conditions are valid.

When VCC voltage falls below 24 V, it is considered as adapter voltage returns back to normal voltage. ACOK is pulled high by an external pullup resistor. BATFET is turned off and ACFET and RBFET is turned on to power the system from the adapter.

System Power Selection

The bq24780S device automatically switches adapter or battery power to system. An automatic break-before-make logic prevents shoot-through currents when the selectors switch.

The ACDRV drives a pair of common-source (CMSRC) N-channel power MOSFETs (ACFET and RBFET) between adapter and ACP. The ACFET separates adapter from system and battery, and provides a limited di/dt when plugging in adapter by controlling the ACFET turn-on time. Meanwhile, it protects the adapter when the system or battery is shorted. The RBFET provides negative input voltage protection and battery discharge protection when adapter is shorted to ground, and minimizes system power dissipation with its low RDS(on) compared to a Schottky diode.

When the adapter is not present, ACDRV is pulled to CMSRC to keep ACFET and RBFET off, disconnecting the adapter from the system. BATDRV stays at VBATSRC + 6 V to connect battery to system if all of the following conditions are valid:

  • VCC > VUVLO
  • VACN < VSRN + 200 mV
  • ACFET/RBFET off

After the adapter plugs in, the system power source switches from battery to adapter if all of the following conditions are valid:

  • ACOK high
  • Not in LEARN mode
  • In LEARN mode and VSRN < battery depletion threshold

The gate drive voltage on ACFET and RBFET is VCMSRC + 6 V. If the ACFET/RBFET have been turned on for 20 ms, and the voltage across gate and source is still less than 5.7 V, ACFET and RBFET are turned off. After 1.3s delay, it resumes turning on ACFET and RBFET. If such a failure is detected seven times within 90 seconds, ACFET/RBFET are latched off and an adapter removal and system shut down is required to force ACDET < 0.6 V to reset the IC. After IC reset from latch off, ACFET/RBFET can be turned on again. After 90 seconds, the failure counter is reset to zero to prevent latch off.

To turn off ACFET/RBFET, one of the following conditions must be valid:

  • In LEARN mode and VSRN is above battery depletion threshold;
  • ACOK low

To limit the adapter inrush current during ACFET turn-on, the Cgs and Cgd external capacitor of ACFET must be carefully selected following the guidelines below:

  • Minimize total capacitance on system
  • Cgs should be 40× or higher than Cgd to avoid ACFET false turn on during adapter hot plug-in
  • Fully turn on ACFET within 20 ms, otherwise, charger IC will consider turn-on failure
  • Check with MOSFET vendor on peak current rating
  • Place 4-kΩ resistor in series with ACDRV, CMSRC, and BATDRV pin to limit inrush current.

Enable and Disable Charging

In charge mode, the following conditions have to be valid to start charge:

  • Charge is enabled through SMBus (REG0x12[0], default is 0, charge enabled)
  • ILIM pin voltage is higher than 120 mV
  • All ChargeCurrent(), ChargeVoltage() and InputCurrent() registers have valid value programmed
  • ACOK is valid (see Device Power Up for details)
  • ACFET and RBFET turn on and gate voltage is high enough (see System Power Selection for details)
  • VSRN does not exceed BATOVP threshold
  • IC temperature does not exceed TSHUT threshold
  • Not in ACOC condition (see Device Protections Features for details)

One of the following conditions stops on-going charging:

  • Charge is inhibited through SMBus(REG0x12[0]=1)
  • ILIM pin voltage is lower than 60 mV
  • One of three registers is set to 0 or out of range
  • ACOK is pulled low (see Device Power Up for details)
  • ACFET turns off
  • VSRN exceeds BATOVP threshold
  • TSHUT IC temperature threshold is reached
  • ACOC is detected (see Device Protections Features for details)
  • Short circuit is detected (see Inductor Short, MOSFET Short Protection for details)
  • Watchdog timer expires if watchdog timer is enabled (see Charger Timeout for details)

Automatic Internal Soft-Start Charger Current

Every time the charge is enabled, the charger automatically applies soft-start on charge current to avoid any overshoot or stress on the output capacitors or the power converter. The charge current starts at 128 mA, and the step size is 64 mA in CCM mode for a 10 mΩ current sensing resistor. Each step lasts around 400 μs in CCM mode, till it reaches the programmed charge current limit. No external components are needed for this function.

During DCM mode, the soft start up current step size is larger and each step lasts for longer time period due to the intrinsic slow response of DCM mode.

Current and Power Monitor

High Accuracy Current Sense Amplifier (IADP and IDCHG)

As an industry standard, a high-accuracy current sense amplifier (CSA) is used to monitor the input current (IADP) and the discharge current (IDCHG). IADP voltage is 20X or 40X the differential voltage across ACP and ACN. IDCHG voltage is 8X or 16X the differential voltage across SRN and SRP. After VCC is above UVLO and ACDET is above 0.6 V, IADP output becomes valid. .

A maximum 100-pF capacitor is recommended to connect on the output for decoupling high-frequency noise. An additional RC filter is optional, if additional filtering is desired. Note that adding filtering also adds additional response delay. The CSA output voltage is clamped at 3.3 V. To lower the voltage on current monitoring, a resistor divider from CSA output to GND can be used and accuracy over temperature can still be achieved

High Accuracy Power Sense Amplifier (PMON)

The bq24780S device monitors total available power from adapter and battery together. The ratio of PMON voltage and total power KPMON can be programmed in REG0x3B[9] with default 1 µA/W. The bq24780S device allows input sense resistor 2x or 1/2x of charge sense resistor by setting REG0x3B[13:12] to 1.

Equation 1. IPMON = KPMON (VIN x IIN - VBAT x IBAT) (IBAT > 0 during charge; IBAT < 0 during discharge)

A resistor is connected on the PMON pin to converter output current to output voltage. A maximum 100-pF capacitor is recommended to connect on the output for decoupling high-frequency noise. An additional RC filter is optional, if additional filtering is desired. Note that adding filtering also adds additional response delay. The PMON output voltage is clamped to 3.3 V.

Processor Hot Indication for CPU Throttling

When CPU is running turbo mode, the peak power may exceed total available power from adapter and battery. The adapter current and battery discharge overshoot, or system voltage drop indicates the system power may be too high. When the adapter or battery is removed, the remaining power source may not support the peak power in turbo mode. The processor hot function in bq24780S monitors these events, and PROCHOT pulse is asserted.

The PROCHOT triggering events include:

  • ICRIT: adapter peak current
  • INOM: adapter average current (110% of input current limit)
  • IDCHG: battery discharge current
  • VSYS: system voltage on SRN for 2s - 4s battery
  • ACOK: upon adapter removal (ACOK pin HIGH to LOW)
  • BATPRES: upon battery removal (BATPRES pin LOW to HIGH)
  • CMPOUT: Independent comparator output (CMPOUT pin HIGH to LOW)

The threshold of ICRIT, IDCHG or VSYS, and the deglitch time of ICRIT, INOM, IDCHG or CMPOUT are programmable through SMBus. Each triggering event can be individually enabled in REG0x3D[6:0].

bq24780S PROCHOT_profile3_lusbw0.gif Figure 6. PROCHOT Profile

When any event in PROCHOT profile is triggered, PROCHOT is asserted low for minimum 10 ms (default REG0x3C[4:3]=10). At the end of the 10 ms, if the PROCHOT event is still active, the pulse gets extended.

During one cycle of PROCHOT, all the triggering events are saved in status register REG0x3A[6:0] for easy test debug and system optimization.

Converter Operation

The synchronous buck PWM converter uses a fixed frequency voltage control scheme and internal type III compensation network. The LC output filter gives a characteristic resonant frequency:

Equation 2. bq24780S eq_fo_SLUSBW0.gif

The resonant frequency, fo, is used to determine the compensation to ensure there is sufficient phase margin for the target bandwidth. The LC output filter should be selected to give a resonant frequency of 10- to 20-kHz nominal for the best performance. Suggested component value for a charge current of 800-kHz default switching frequency is shown in Table 1:

Table 1. Suggest Component Value for Charge Current of 800-kHz Default Switching Frequency

CHARGE CURRENT2A3A4A6A8A
Output Inductor Lo (µH)6.8 or 8.25.6 or 6.83.3 or 4.73.32.2
Output Capacitor Co (µF)2020203040
Sense Resistor (mΩ)1010101010

Ceramic capacitors show a DC-bias effect. This effect reduces the effective capacitance when a DC-bias voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data sheet about the performance with a DC bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value to get the required value at the operating point.

Continuous Conduction Mode (CCM)

With sufficient charge current, the inductor current does not cross 0, which is defined as CCM. The controller starts a new cycle with ramp coming up from 200 mV. As long as EAO voltage is above the ramp voltage, the high-side MOSFET (HSFET) stays on. When the ramp voltage exceeds EAO voltage, HSFET turns off and low-side MOSFET (LSFET) turns on. At the end of the cycle, ramp gets reset and LSFET turns off, ready for the next cycle. There is always break-before-make logic during transition to prevent cross-conduction and shoot-through. During the dead time when both MOSFETs are off, the body-diode of the low-side power MOSFET conducts the inductor current.

During CCM, the inductor current always flows and creates a fixed two-pole system. Having the LSFET turn-on keeps the power dissipation low and allows safe charging at high currents.

Discontinuous Conduction Mode (DCM)

During the HSFET off time when LSFET is on, the inductor current decreases. If the current goes to 0, the converter enters DCM. Every cycle, when the voltage across SRP and SRN falls below 5 mV (0.5 A on 10 mΩ), the undercurrent-protection comparator (UCP) turns off LSFET to avoid negative inductor current, which may boost the system through the body diode of HSFET.

During DCM the loop response automatically changes. It changes to a single-pole system and the pole is proportional to the load current.

Non-Sync Mode and Light Load Comparator

As the charge current is below 125 mA (on 10-mΩ sense resistor), the light load comparator keeps LSFET off. The converter enters non-sync mode. With LSFET, body diode blocks negative current in the inductor so that no current flows back to the input. As charge current rises above 250 mA, LSFET turns on again.

EMI Switching Frequency Adjust

The charger switching frequency can be adjusted 600 kHz or 1 MHz to solve EMI issues through SMBus command REG0x12[9:8].

Battery LEARN Cycle

A battery LEARN cycle can be activated through the REG0x12[5]. When LEARN is enabled, the system receives power from the battery instead of the adapter turning off ACFET/RBFET and turning on BATFET. The LEARN function allows the battery to discharge in order to calibrate the battery gas gauge over a complete discharge and charge cycle. The controller automatically exits the LEARN cycle when the battery voltage is below the battery depletion threshold. The system switches back to adapter input by turning off BATFET and turning on ACFET/RBFET. After the LEARN cycle, REG0x12[5] is automatically reset to 0.

When the battery is removed during LEARN mode, BATPRES rises from low to high and the device exits LEARN mode. ACFET/RBFET quickly turns on in 100µs to prevent the system from crashing. The turn-on triggered by BATPRES is faster than that triggered by battery depletion comparator.

Charger Timeout

The bq24780S device includes a watchdog timer to terminate charging or hybrid power boost mode if the charger does not receive a write ChargeVoltage() or write ChargeCurrent() command within 175 s (adjustable through 0x12[14:13] command).

If a watchdog timeout occurs, all register values keep unchanged, but converter is suspended. A write to ChargeVoltage(), or ChargeCurrent(), or change REG0x12[14:13] resets watchdog timer and resumes converter for charging or hybrid power boost mode. The watchdog timer can be disabled, or set to 5, 88, or 175 s through SMBus command REG0x12[14:13]).

Device Protections Features

Input Overcurrent Protection (ACOC)

The bq24780S device cannot maintain the input current level if the charge current has been already reduced to 0. When the input current exceeds 1.25x or 2x of ICRIT set point (with 12-ms blank-out time), ACFET/RBFET is latches off and an adapter removal is required to force ACDET < 0.6 V to reset IC. After IC reset from latch off, ACFET/RBFET can be turned on again.

The ACOC function threshold can be set to 1.25x or 2x of ICRIT (REG37[9]) current or disabled through SMBus command (REG0x37[10]).

Charge Overcurrent Protection (CHGOCP)

The bq24780S device has cycle-by-cycle peak overcurrent protection. It monitors the voltage across SRP and SRN, and prevents the current from exceeding the threshold based on the charge current set point. The high-side gate drive turns off for the rest of the cycle when over current is detected, and resumes when the next cycle starts.

The charge OCP threshold is automatically set to 6, 9, and 12 A on a 10-mΩ current sensing resistor based on charge current register value. This prevents the threshold from being too high, which is not safe, or too low, which can be triggered in typical operation. Select proper inductance to prevent OCP triggering in typical operation due to high inductor current ripple.

Battery Overvoltage Protection (BATOVP)

The bq24780S device does not allow the high-side and low-side MOSFET to turn-on when the battery voltage at SRN exceeds 104% of the regulation voltage set point. If BATOVP lasts over 30 ms, charger is completely disabled. This allows a quick response to an overvoltage condition – such as when the load is removed or the battery is disconnected. A 6-mA current sink from SRP to GND is only on during BATOVP and allows discharging the stored output inductor energy that is transferred to the output capacitors.

Battery Short

When battery voltage on SRN falls below 2.5 V, the converter resets for 1 ms and resumes charge if all the enable conditions in the Enable and Disable Charging section are satisfied. This prevents overshoot current in the inductor, which can saturate the inductor and may damage the MOSFET. The charge current is limited to 0.5 A on 10-mΩ current sensing resistor when BATLOWV condition persists and LSFET keeps off. The LSFET turns on only for a refreshing pulse to charge BTST capacitor.

Thermal Shutdown Protection (TSHUT)

The WQFN package has low thermal impedance, which provides good thermal conduction from the silicon to the ambient, to keep junction temperatures low. As an added level of protection, the charger converter turns off for self-protection whenever the junction temperature exceeds the 155°C. The charger stays off until the junction temperature falls below 135°C. During thermal shutdown, the REGN LDO current limit is reduced to 14 mA. Once the temperature falls below 135°C, charge can be resumed with soft start.

Inductor Short, MOSFET Short Protection

The bq24780S device has a unique short circuit protection feature. Its cycle-by-cycle current monitoring feature is achieved through monitoring the voltage drop across RDS(on) of the MOSFETs after a certain amount of blanking time. In case of a MOSFET short or inductor short circuit, the overcurrent condition is sensed by two comparators and two counters are triggered. After seven short circuit events, the charger is latched off and ACFET and RBFET are turned off to disconnect the adapter from the system. BATFET is turned on to connect the battery pack to the system. To reset the charger from latch-off status, the IC VCC pin must be pulled below UVLO or the ACDET pin must be pulled below 0.6 V. This can be achieved by removing the adapter and shutting down the operation system. The low-side MOSFET Vds monitor circuit is enabled by REG0x37[7], and the threshold is 750 mV. The high-side MOSFET Vds monitor circuit is enabled by REG0x37[6], and the threshold is 250 mV. During boost function, the low-side MOSFET short circuit protection threshold is used for cycle-by-cycle current limiting, charger does not latch up.

Due to the amount of blanking time to prevent noise when MOSFET just turns on, the cycle-by-cycle charge overcurrent protection may detect high current and turn off MOSFET first before the short circuit protection circuit can detect short condition because the blanking time has not finished. In such a case, the charger may not be able to detect a short circuit and the counter may not be able to count to seven then latch off. Instead the charger may continuously keep switching with very narrow duty cycle to limit the cycle-by-cycle current peak value. However, the charger should still be safe and does not cause failure because the duty cycle is limited to a very short time and the MOSFET should still be inside the safety operation area. During a soft start period, it may take a long time instead of just seven switching cycles to detect short circuit based on the same blanking time reason.

Device Functional Modes

Battery Charging

The bq24780S charges 1-4 cell battery in constant current (CC), and constant voltage (CV) mode. The host programs battery voltage in REG0x15(). According to battery voltage, the host programs appropriate charge current in REG0x14(). When battery is full or battery is not in good condition to charge, host terminates charge by setting REG0x12[0] to 1, or setting either ChargeVoltage() or ChargeCurrent() to zero.

See the Feature Description section for details on charge enable conditions and register programming.

Hybrid Power Boost Mode

The bq24780S device supports the hybrid power boost mode by allowing battery discharge energy to system when system power demand is temporarily higher than adapter maximum power level so the adapter does not crash. After device powers up, the REG0x37[2] is 0 to disable hybrid power boost mode. To enable hybrid power boost mode, host writes 1 to REG0x37[2]. The TB_STAT pin and REG0x37[1] indicate if the device is in hybrid power boost mode.

To support hybrid power boost mode, input current must be set higher than 1536 mA for 10 mΩ input current sensing resistor. When input current is higher than 107% of input current limit in REG0x3F(), charger IC allows battery discharge and charger converter changes from buck converter to boost converter. During hybrid power boost mode the adapter current is regulated at input current limit level so that adapter will not crash. The battery discharge current depends on system current requirement and adapter current limit. The watchdog timer can be enabled to prevent converter running at hybrid power boost mode for too long.

Battery Discharge Current Regulation in Hybrid Power Boost Mode

To keep the discharge current below battery OCP rating during boost mode, the bq24780S device supports discharge current regulation. After device powers up, the REG0x37[15] is 0 to disable discharge current regulation. To enable discharge current regulation, host writes 1 to REG0x37[15].

Once the battery discharge current is limited, the input current goes up to meet the system current requirement. The user can assert PROCHOT to detect input current increase (ICRIT or INOM), and request CPU throttling to lower the system power.

Programming

SMBus Interface

The bq24780S device operates as a slave, receiving control inputs from the embedded controller host through the SMBus interface. The bq24780S device uses a simplified subset of the commands documented in System Management Bus Specification V1.1, which can be downloaded from www.smbus.org. The bq24780S device uses the SMBus read-word and write-word protocols (shown in Table 2 and Table 3) to communicate with the smart battery. The bq24780S device performs only as a SMBus slave device with address 0b00010010 (0x12H) and does not initiate communication on the bus. In addition, the device has two identification registers, a 16-bit device ID register (0xFFH) and a 16-bit manufacturer ID register (0xFEH).

SMBus communication starts when VCC is above UVLO.

The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose pullup resistors (10 kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications. Communication starts when the master signals a start condition, which is a high-to-low transition on SDA, while SCL is high. When the master has finished communicating, the master issues a stop condition, which is a low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 7 and Figure 8 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and data bytes are transmitted between the start and stop conditions. The SDA state changes only while SCL is low, except for the start and stop conditions. Data is transmitted in 8-bit bytes and is sampled on the rising edge of SCL. Nine clock cycles are required to transfer each byte in or out of the bq24780S device because either the master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle. The bq24780S supports the charger commands listed in Table 2.

SMBus Write-Word and Read-Word Protocols

Table 2. Write-Word Format

S
(1)(3)
SLAVE ADDRESS(1)W
(1)(6)
ACK
(2)(5)
COMMAND BYTE(1)ACK
(2)(5)
LOW DATA BYTE(1)ACK
(2)(5)
HIGH DATA BYTE(1)ACK
(2)(5)
P
(1)(4)
7 bits1b1b8 bits1b8 bits1b8 bits1b
MSB LSB00MSB LSB0MSB LSB0MSB LSB0
Master to slave
Slave to master (shaded gray)
S = Start condition or repeated start condition
P = Stop condition
ACK = Acknowledge (logic-low)
W = Write bit (logic-low)

Table 3. Read-Word Format

S(1)(3)SLAVE ADDRESS(1)W
(1)(7)
ACK
(2)(5)
COMMAND BYTE(1)ACK
(2)(5)
S(1)(3)SLAVE ADDRESS(1)R(1)(8)ACK
(2)(5)
LOW DATA BYTE(2)ACK
(1)(5)
HIGH DATA BYTE(2)NACK
(1)(6)
P
(1)(4)
7 bits1b1b8 bits1b7 bits1b1b8 bits1b8 bits1b
MSB LSB00MSB LSB0MSB LSB10MSB LSB0MSB LSB1
Master to slave
Slave to master (shaded gray)
S = Start condition or repeated start condition
P = Stop condition
ACK = Acknowledge (logic-low)
NACK = Not acknowledge (logic-high)
W = Write bit (logic-low)
R = Read bit (logic-high)

Timing Diagrams

bq24780S timing_write_SLUSBW0.gif
A = Start conditionH = LSB of data clocked into slave
B = MSB of address clocked into slaveI = Slave pulls SMBDATA line low
C = LSB of address clocked into slaveJ = Acknowledge clocked into master
D = R/W bit clocked into slaveK = Acknowledge clock pulse
E = Slave pulls SMBDATA line lowL = Stop condition, data executed by slave
F = ACKNOWLEDGE bit clocked into masterM = New start condition
G = MSB of data clocked into slave
Figure 7. SMBus Write Timing
bq24780S timing_read_SLUSBW0.gif
A = Start conditionG = MSB of data clocked into master
B = MSB of address clocked into slaveH = LSB of data clocked into master
C = LSB of address clocked into slaveI = Acknowledge clock pulse
D = R/W bit clocked into slaveJ = Stop condition
E = Slave pulls SMBDATA line lowK = New start condition
F = ACKNOWLEDGE bit clocked into master
Figure 8. SMBus Read Timing

Register Maps

Battery-Charger Commands

The bq24780S supports thirteen battery-charger commands that use either Write-Word or Read-Word protocols, as summarized in Table 4. ManufacturerID() and DeviceID() can be used to identify the bq24780S. The ManufacturerID() command always returns 0x0040H and the DeviceID() command always returns 0x0030H.

Table 4. Battery Charger Command Summary

REGISTER ADDRESSREGISTER NAMEREAD OR WRITEDESCRIPTIONPOR STATE
0x12HChargeOption0() Table 5Read or WriteCharge Options Control 00xE108H
0x3BHChargeOption1() Table 6Read or WriteCharge Options Control 10xC210H
0x38HChargeOption2()Table 7Read or WriteCharge Options Control 20x0384H
0x37HChargeOption3()Table 8Read or WriteCharge Options Control 30x1A40H
0x3CHProchotOption0()Table 9Read or WritePROCHOT Options Control 00x4A54H
0x3DHProchotOption1() Table 10Read or WritePROCHOT Options Control 10x8120H
0x3AHProchotStatus() Table 11Read OnlyPROCHOT status0x0000H
0x14HChargeCurrent() Table 12Read or Write7-bit Charge Current Setting0x0000H
0x15HChargeVoltage() Table 13Read or Write11-bit Charge Voltage Setting0x0000H
0x39HDischargeCurrent() Table 15Read or Write6-bit Discharge Current Setting0x1800H, or 6144mA
0x3FHInputCurrent() Table 14Read or Write6-bit Input Current Setting0x1000H, or 4096mA
0xFEHManufacturerID() Read OnlyManufacturer ID0x0040H
0xFFHDeviceID() Read OnlyDevice ID0x30H

Setting Charger Options

ChargeOption0 Register

Figure 9. ChargeOption0 Register (0x12H)
15141312111098
Low Power Mode EnableWATCHDOG Timer AdjustReservedSwitching Frequency
R/WR/WRR/W
76543210
ReservedLEARN Mode EnableIADP Amplifier Gain for Primary InputIDCHG Amplifier RatioReservedCharge Inhibit
RR/WR/WR/WRR/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5. ChargeOption0 Register (0x12H)

BITBIT NAMEDESCRIPTION
[15]Low Power Mode Enable
(EN_LWPWR)
0: IC in performance mode with battery only. The PROCHOT, current/power monitor buffer and independent comparator follow register setting.
1: IC in low power mode with battery only. IC is in the lowest quiescent current when this bit is enabled. PROCHOT, discharge current monitor buffer, power monitor buffer and independent comparator are disabled (default at POR)
[14:13]WATCHDOG Timer Adjust
(WDTMR_ADJ)
Set maximum delay between consecutive SMBus write charge voltage or charge current command.
If IC does not receive write on REG0x14() or REG0x15() within the watchdog time period, the charger converter stops to disable charge and boost mode operation.
After expiration, the timer will resume upon the write of REG0x14() or REG0x15(). The charge or boost operation will resume if all the other conditions are valid.
00: Disable watchdog timer
01: Enabled, 5 sec
10: Enabled, 88 sec
11: Enable watchdog timer (175 s) (default at POR)
[12:10]Reserved0 - Reserved
[9:8]Switching Frequency
(PWM_FREQ)
Converter switching frequency.
00: 600 kHz
01: 800 kHz (default at POR)
10: 1 MHz
11: Reserved
[7:6]Reserved 0 - Reserved
[5]LEARN Mode Enable
(EN_LEARN)
Battery LEARN mode enable. In LEARN mode, ACFET and RBFET turns off and BATFET turns on. When /BATPRES is HIGH, IC exits LEARN mode and this bit is set back to 0. When the battery is depleted, the charger cannot enable LEARN mode
0: Disable LEARN mode (default at POR)
1: Enable LEARN mode
[4]IADP Amplifier Gain for Primary Input
(IADP_GAIN)
Ratio of IADP pin voltage over the voltage across ACP and ACN.
0: 20X (default at POR)
1: 40X
[3]IDCHG Amplifier Gain
(IDCHG_GAIN)
Ratio of IDCHG pin voltage over the voltage across SRN and SRP. 0: 8x with discharge current regulation range 0-32A.
0: 8x with discharge current regulation range 0-32A.
1: 16x with discharge current regulation range (default at POR)
[2:1]Reserved0 - Reserved
[0] Charge Inhibit
(CHRG_INHIBIT)
Charge inhibit. When this bit is 0, battery charging is enabled with valid value in REG0x14() and REG0x15()
0: Enable charge (default at POR)
1: Inhibit charge

ChargeOption1 Register

Figure 10. ChargeOption1 Register (0x3BH)
15141312111098
BAT Depletion Comparator ThresholdInput/Discharge Sense Resistor Ratio REN_IDCHGEN_PMONPMON GainReserved
R/WR/WR/WR/WR/WR
76543210
Independent Comparator ReferenceIndependent Comparator PolarityIndependent Comparator Deglitch TimePower Path Latch-off EnableReservedDischarge SRN for Shipping Mode_EN Reserved
R/WR/WR/WR/WRR/WR
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6. ChargeOption1 Register (0x3BH)

BITBIT NAMEDESCRIPTION
[15:14]Battery Depletion Threshold (BAT_DEPL_VTH)Battery over-discharge threshold.During LEARN cycle, when battery voltage is below the depletion threshold, the IC exits LEARN mode. During boost mode, when battery voltage is below the depletion threshold, the IC exits boost mode.
00: Falling threshold = 59.19% of voltage regulation limit (~2.486V/cell)
01: Falling threshold = 62.65% of voltage regulation limit (~2.631V/cell)
10: Falling threshold = 66.55% of voltage regulation limit (~2.795V/cell)
11: Falling threshold = 70.97% of voltage regulation limit (2.981V/cell) (default at POR)
[13:12](RSNS_RATIO) 0 - Adjust the PMON calculation with different input sense resistor RAC and charge sense resistor RSR.
00: RAC and RSR
1:1 (default at POR)
01: RAC and RSR 2:1
10: RAC and RSR 1:2
11: Reserved
[11]EN_IDCHGIDCHG pin output enable.
0: Disable IDCHG output to minimize Iq (default at POR)
1: Enable IDCHG output
[10]EN_PMON PMON pin output enable.
0: Disable PMON output to minimize Iq (default at POR)
1: Enable PMON output
[9]PMON Gain
(PMON_RATIO)
Ratio of PMON output current vs total input and battery power with 10 mΩ sense resistor.
0: 0.25 µA/W
1: 1 µA/W (default at POR)
With the sense resistor is 20/10 mΩ, or 10/20 mΩ, or 20/20mΩ (RAC and RSR)
0: 0.5 µA/W
1: 2 µA/W (default at POR)
[8]Reserved0 - Reserved
[7]Independent Comparator Reference (CMP_REF) Independent comparator internal reference.
0: 2.3 V (default at POR)
1: 1.2 V
[6]Independent Comparator Polarity (CMP_POL)Independent comparator output polarity
0: When CMPIN is above internal threshold, CMPOUT is LOW (default at POR)
1: When CMPIN is above internal threshold, CMPOUT is HIGH
[5:4]Independent Comparator Deglitch Time (CMP_DEG) Independent comparator deglitch time, applied on the edge where CMPOUT goes LOW. No deglitch time is applied on the rising edge of CMPOUT.
00: Independent comparator is disabled
01: Independent comparator is enabled with output deglitch time 1 µs  (default at POR)
10: Independent comparator is enabled with output deglitch time 2 ms
11: Independent comparator is enabled with output deglitch time 5 sec
[3]Power Path Latch-off Enable (EN_FET_LATCHOFF )When independent comparator is triggered, both ACFET/RBFET turn off. The latch off is cleared by either POR or write this bit to zero.
0: When independent comparator is triggered, no power path latch off (default at POR)
1: When independent comparator is triggered, power path latches off.
[2]Reserved0 - Reserved
[1]Discharge SRN for Shipping Mode (EN_SHIP_DCHG) Discharge SRN pin for 140 ms with minimum 5-mA current. When 140 ms is over, this bit is reset to 0.
0 : Disable discharge mode (default at POR)
1: Enable discharge mode
[0]Reserved0 - Reserved

ChargeOption2 Register

Figure 11. ChargeOption2 Register (0x38H)
15141312111098
ReservedReserved
RR
76543210
Independent External Current Limit Enable ReservedReservedReserved
R/WRRR
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. ChargeOption2 Register (0x38H)

BITBIT NAMEDESCRIPTION
[15:10]Reserved0 – Reserved
[9:8]Reserved1 - Reserved
[7]External Current Limit Enable (EN_EXTILIM) External ILIM pin enable to set the charge and discharge current.
0: Charge/discharge current limit is set by REG0x14() and 0x39().
1: Charge/discharge current limit is set by the lower value of ILIM pin and registers. (default at POR)
[6:3]Reserved0 - Reserved
[2]Reserved1 - Reserved
[1:0]Reserved0 - Reserved

ChargeOption3 Register

Figure 12. ChargeOption3 Register (0x37H)
15141312111098
Discharge Current Regulation EnableReservedACOK Deglitch Time for Primary InputAdapter Present Indicator ACOC EnableACOC LimitReserved
R/WRR/WR/WR/WR/WR
76543210
HSFET VDS Threshold LSFET VDS Threshold Fast DPM ThresholdFast DPM Deglitch TimeHybrid Power Boost Mode EnableBoost Mode IndicationReserved
R/WR/WR/WR/WR/WR/WR
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8. ChargeOption3 Register (0x37H)

BITBIT NAMEDESCRIPTION
[15]Discharge Current Regulation Enable(EN_IDCHG_REG)Battery discharge current regulation enable.
0: Disable discharge current regulation (default at POR)
1: Enable discharge current regulation
[14:13]Reserved0 - Reserved
[12]ACOK Deglitch Time for Primary Input (ACOK_DEG ) Adjust ACOK rising edge deglitch time.
After POR, the first time adapter plugs in, deglitch time is always 150 ms regardless of register bit. Starting from the 2nd time adapter plugs in, the deglitch time follows the bit setting. During system over-current, or system short when ACDET is pulled below 2.4 V, 1.3 sec deglitch time keeps ACFET/RBFET turn off long enough before the next turn on.
0: ACOK rising edge deglitch time 150ms
1: ACOK rising edge deglitch time 1.3 sec (default at POR)
[11]Adapter Present Indicator (ACOK_STAT )
Input present indicator. Same logic as ACOK pin. This bit is read only.
0: AC adapter is not present
1: AC adapter is present
[10]ACOC Enable (EN_ACOC)ACOC protection threshold by monitoring ACP_ACN voltage.
0: Disable ACOC (default at POR)
1: Enable ACOC
[9]ACOC Limit (ACOC_VTH)ACOC protection threshold by monitoring ACP_ACN voltage.
0: 125% of ICRIT
1: 200% of ICRIT (default at POR)
[8]Reserved0 – Reserved
[7]HSFET VDS Threshold (IFAULT_HI)MOSFET/inductor short protection by monitoring high side MOSFET drain-source voltage.
0: Disable (default at POR)
1: 750 mV
[6]LSFET VDS Threshold (IFAULT_LO)MOSFET/inductor short protection by monitoring low side MOSFET drain-source voltage. Also as cycle-by-cycle current limit protection threshold during boost function.
0: Disable
1: 250 mV (default at POR)
[5]Fast DPM Threshold (FDPM_VTH)Fast DPM comparator threshold to enter hybrid power boost mode. (Minimum DPM setting for boost mode: 1536 mA)
0: 107% (falling 93%)(<default at POR)
1: 115% (falling 85%)
[4:3]Fast DPM Deglitch Time (FDPM_DEG)Response time from system current exceeding Fast DPM Threshold to battery discharge in boost mode.
00: Response time 150 µs (default at POR)
01: Response time 250 µs
1X: Response time 50 µs
[2]Hybrid Power Boost Mode Enable (EN_BOOST)Boost mode enable bit. When /BATPRES goes from LOW to HIGH (battery removal), this bit will be reset to zero to disable boost mode.
0: Disable hybrid power boost mode (default at POR)
1: Enable hybrid power boost mode
[1]Boost Mode Indication (BOOST_STAT)In boost mode indicator. It goes LOW when the device is in boost mode. This bit is read only.
0: Charger is not in hybrid power boost mode (default at POR)
1: Charger is in hybrid power boost mode
[0]Reserved0 – Reserved

ProchotOption0 Register

Figure 13. ProchotOption0 Register (0x3CH)
15141312111098
ICRIT ThresholdICRIT Deglitch timeReserved
R/WR/WR
76543210
VSYS ThresholdPROCHOT Pulse Extension EnablePROCHOT Pulse WidthPROCHOT Pulse ClearPROCHOT Pulse Clear INOM Deglitch TimeReserved
R/WR/WR/WR/WR/WR/WR
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. ProchotOption0 Register (0x3CH)

BITBIT NAMEDESCRIPTION
[15:11]ICRIT Threshold (ICRIT_VTH) 5 bits, percentage of IDPM in REG0x3F(). Measure current through ACP and ACN. Trigger when the current is above this threshold.
00000:110%
00001: 110%
00010: 115%
00011: 120%
….
10010: 195%
10011: 200%
10100: 205%
10101: 210%
10110: 215%
10111: 220%
11000: 225%
11001: 230%
11010: 250%
11011: 300%
11100: 350%
11101: 400%
11110: 450%
11111: Out of Range
Step: 5%, Default 150% (01001)
[10:9]ICRIT Deglitch time (ICRIT_DEG)Typical ICRIT deglitch time.
00: 10 µs
01: 100 µs (default at POR)
10: 400 µs
11: 800 µs
[8]Reserved0 – Reserved
[7:6]VSYS Threshold (VSYS_VTH)Measure on SRN with fixed 20-µs deglitch time. Trigger when SRN voltage is below the threshold.
If REG0x15() is programmed below VSYS threshold, it is recommended to not enable VSYS in PROCHOT profile.
00: 5.75 V
01: 6 V (default at POR)
10: 6.25 V
11: 6.5 V
[5]PROCHOT Pulse Extension Enable (EN_PROCHOT_EXT)When pulse extension is enabled, keep PROCHOT pin voltage low until host write 0x3C[2] = 0.
0: Disable pulse extension (default at POR)
1: Enable pulse extension
[4:3]PROCHOT Pulse Width (PROCHOT_WIDTH)Minimum PROCHOT pulse width when REG0x3C[5]=0
00: 100 µs
01: 1 ms
10: 10 ms (default at POR)
11: 5 ms
[2]PROCHOT Pulse Clear (PROCHOT_CLEAR)Clear PROCHOT pulse when (0x3C[5] = 1).
0: Clear PROCHOT pulse and drive PROCHOT pin HIGH
1: Idle (default at POR)
[1]INOM Deglitch Time (INOM_DEG)Maximum INOM deglitch time. INOM threshold is 110% of IDPM in REG0x3F(). Measure current between ACP and ACN. Trigger when the current is above this threshold.
0: 1 ms (has to be max) (default at POR)
1: 60 ms (max)
[0]Reserved0 - Reserved

ProchotOption1 Register

Figure 14. ProchotOption1 Register (0x3DH)
15141312111098
IDCHG ThresholdIDCHG comparator deglitch time
R/WR/W
76543210
ReservedPROCHOT input current envelop selector
RR/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10. ProchotOption1 Register (0x3DH)

BITBIT NAMEDESCRIPTION
[15:10]IDCHG Threshold (IDCHG_VTH)6 bit, range, range  0 A to 32256 mA, step 512 mA. Measure current between SRN and SRP. Trigger when the discharge current is above the threshold.
Default: 16384 mA (100000)
[9:8]IDCHG Deglitch Time (IDCHG_DEG)Typical IDCHG deglitch time.
00: 1.6 ms
01: 100 µs (default at POR)
10: 6 ms
11: 12 ms
[7]Reserved0 - Reserved
[6:0]PROCHOT input current envelop selector (PROFILE) When adapter is present, the PROCHOT function is enabled by the below bits.
When adapter is removed, ICRIT, INOM, BATPRES, and ACOK functions are automatically disabled in the PROCHOT profile. Comparator, IDCHG, and VSYS function settings are preserved. When all the bits are 0, PROCHOT function is disabled.
Bit 6: Independent comparator, 0: disable (default at POR); 1: enable
Bit 5: ICRIT, 0: disable; 1: enable (default at POR)
Bit 4: INOM, 0: disable (default at POR); 1: enable
Bit 3: IDCHG, 0: disable (default at POR); 1: enable
Bit 2: VSYS, 0: disable (default at POR); 1: enable
Bit 1: BATPRES, 0: disable (default at POR) ; 1: enable (one-shot rising edge triggered)
Bit 0: ACOK, 0: disable (default at POR) ; 1: enable (one-shot falling edge triggered)

ProchotStatus Register

Figure 15. ProchotStatus Register (0x3AH)
15141312111098
Reserved
R/W
76543210
ReservedPROCHOT status
R/WR
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11. ProchotStatus Register (0x3AH)

BITBIT NAMEDESCRIPTION
[15:7]Reserved0 - Reserved
[6:0]PROCHOT status (Read only)The status of all events triggered during the same PROCHOT pulse are set to 1. The register resets when either of below two conditions occurs.
  • Host first read after PROCHOT goes high
  • PROCHOT goes low to start another pulse.

Bit 6: Independent comparator, 0: Not triggered; 1: Triggered
Bit 5: ICRIT, 0: Not triggered; 1: Triggered
Bit 4: INOM, 0: Not triggered; 1: Triggered
Bit 3: IDCHG, 0: Not triggered; 1: Triggered
Bit 2: VSYS, 0: Not triggered; 1: Triggered
Bit 1: BATPRES, 0: Not triggered ; 1: Triggered
Bit 0: ACOK, 0: Not triggered ; 1: Triggered

Setting the Charge Current

To set the charge current, write a 16-bit ChargeCurrent() command (0x14H or 0b00010100) using the data format listed in Table 12. With 10-mΩ sense resistor, the bq24780S device provides a charge current range of 128 mA to 8.128 A, with 64-mA step resolution. Upon POR, charge current is 0 A. Any conditions for ACOK low except ACOV resets the ChargeCurrent() to 0. Sending ChargeCurrent() 0 mA terminates charge.

To provide secondary protection, the bq24780S has an ILIM pin with which the user can program the maximum allowed charge current. Internal charge current limit is the lower one between the voltage set by ChargeCurrent(), and the voltage on ILIM pin. To disable this function, the user can pull ILIM above 2 V, which is the maximum charge current regulation limit. When ILIM is below 60 mV, battery charging is disabled. The preferred charge current limit can be derived from below equation:

Equation 3. bq24780S eq_Ichg_SLUSBW0.gif

The SRP and SRN pins are used to sense RSR with default value of 10 mΩ. However, resistors of other values can also be used. For a larger sense resistor, a larger sense voltage is given, and a higher regulation accuracy; but, at the expense of higher conduction loss. If current sensing resistor value is too high, it may trigger an overcurrent protection threshold because the current ripple voltage is too high. In such a case, either a higher inductance value or a lower current sensing resistor value should be used to limit the current ripple voltage level. A current sensing resistor value no more than 20 mΩ is suggested.

Table 12. Charge Current Register (0x14H), Using 10-mΩ Sense Resistor

BITBIT NAMEDESCRIPTION
0Not used; value ignored
1Not used; value ignored
2Not used; value ignored
3Not used; value ignored
4Not used; value ignored
5Not used; value ignored
6Charge Current, DACICHG 00 = Adds 0 mA of charger current
1 = Adds 64 mA of charger current
7Charge Current, DACICHG 10 = Adds 0 mA of charger current
1 = Adds 128 mA of charger current
8Charge Current, DACICHG 20 = Adds 0 mA of charger current
1 = Adds 256 mA of charger current
9Charge Current, DACICHG 30 = Adds 0 mA of charger current
1 = Adds 512 mA of charger current
10Charge Current, DACICHG 40 = Adds 0 mA of charger current
1 = Adds 1024 mA of charger current
11Charge Current, DACICHG 50 = Adds 0 mA of charger current
1 = Adds 2048 mA of charger current
12Charge Current, DACICHG 60 = Adds 0 mA of charger current
1 = Adds 4096 mA of charger current
13Not used; 1 = invalid write
14Not used; 1 = invalid write
15Not used; 1 = invalid write

Setting the Charge Voltage

To set the output charge regulation voltage, write a 16-bit ChargeVoltage() command (0x15H or 0b00010101) using the data format listed in Table 13. The bq24780S device provides charge voltage range from 1.024 to 19.200 V, with 16-mV step resolution. Upon POR, charge voltage limit is 0 V. Sending ChargeVoltage() 0 mV terminates charge.

The SRN pin is used to sense the battery voltage for voltage regulation and should be connected as close to the battery as possible, and directly place a decoupling capacitor (0.1 µF recommended) as close to IC as possible to decouple high frequency noise.

Table 13. Charge Voltage Register (0x15H)

BITBIT NAMEDESCRIPTION
0Not used; value ignored
1Not used; value ignored
2Not used; value ignored
3Not used; value ignored
4Charge voltage, DACV 00 = Adds 0 mV of charger voltage
1 = Adds 16 mV of charger voltage
5Charge voltage, DACV 10 = Adds 0 mV of charger voltage
1 = Adds 32 mV of charger voltage
6Charge voltage, DACV 20 = Adds 0 mV of charger voltage
1 = Adds 64 mV of charger voltage
7Charge voltage, DACV 30 = Adds 0 mV of charger voltage
1 = Adds 128 mV of charger voltage
8Charge voltage, DACV 40 = Adds 0 mV of charger voltage
1 = Adds 256 mV of charger voltage
9Charge voltage, DACV 50 = Adds 0 mV of charger voltage
1 = Adds 512 mV of charger voltage
10Charge voltage, DACV 60 = Adds 0 mV of charger voltage
1 = Adds 1024 mV of charger voltage
11Charge voltage, DACV 70 = Adds 0 mV of charger voltage
1 = Adds 2048 mV of charger voltage
12Charge voltage, DACV 80 = Adds 0 mV of charger voltage
1 = Adds 4096 mV of charger voltage
13Charge voltage, DACV 90 = Adds 0 mV of charger voltage
1 = Adds 8192 mV of charger voltage
14Charge voltage, DACV 100 = Adds 0 mV of charger voltage
1 = Adds 16384 mV of charger voltage
15Not used; 1 = invalid write

Setting Input Current

System current normally fluctuates as portions of the system are powered-up or put to sleep. With the input current limit, the output current requirement of the AC wall adapter can be regulated its rating, reducing system cost.

The total input current, from a wall cube or other DC source, is the sum of the system supply current and the current required by the charger. When the input current exceeds the set input current limit, the bq24780S device decreases the charge current to provide priority to system load. As the system current rises, the available charge current drops linearly to 0. Thereafter, charger goes into hybrid power boost mode and adds battery power to support system load. During turbo-boost mode, input current stays in regulation.

During DPM regulation, the total input current is the sum of the device supply current IBIAS, the charger input current, and the system load current ILOAD, and can be estimated as follows:

Equation 4. bq24780S eq_Iinput_SLUSBW0.gif

In the above equation, η is the efficiency the switching regulator and IBATTERY is the battery charging or discharging current (positive for charging and negative for discharging). In charging mode, the charger converter is in buck configuration. In turbo-boost mode, the charger converter is in boost configuration.

To set the input current limit, write a 16-bit InputCurrent() command (0x3FH or 0b00111111) using the data format listed in Table 14. When using a 10-mΩ sense resistor, the bq24780S device provides an input-current limit range of 128 mA to 8.064 A, with 128-mA resolution. Upon POR, default input current limit is 4096 mA on 10-mΩ current sensing resistor (RAC).

The ACP and ACN pins are used to sense RAC with default value of 10 mΩ. However, resistors of other values can also be used. For a larger sense resistor, larger sense voltage is given, and higher regulation accuracy, but at the expense of higher conduction loss.

Table 14. Input Current Register (0x3FH), Using 10-mΩ Sense Resistor

BITBIT NAMEDESCRIPTION
0Not used; value ignored
1Not used; value ignored
2Not used; value ignored
3Not used; value ignored
4Not used; value ignored
5Not used; value ignored
6Not used; value ignored
7Input current, DACIIN 00 = Adds 0 mA of input current
1 = Adds 128 mA of input current
8Input current, DACIIN 10 = Adds 0 mA of input current
1 = Adds 256 mA of input current
9Input current, DACIIN 20 = Adds 0 mA of input current
1 = Adds 512 mA of input current
10Input current, DACIIN 30 = Adds 0 mA of input current
1 = Adds 1024 mA of input current
11Input current, DACIIN 40 = Adds 0 mA of input current
1 = Adds 2048 mA of input current
12Input current, DACIIN 50 = Adds 0 mA of input current
1 = Adds 4096 mA of input current
13Not used; 1 = invalid write
14Not used; 1 = invalid write
15Not used; 1 = invalid write

Setting the Discharge Current

To set the discharging current limit, write a 16-bit DischargeCurrent() command (0x39H or 0b00111111) using the data format listed in Table 15. When using a 10-mΩ sense resistor, the bq24780S device provides a discharge current limit range of 512 mA to 32.256 A, with 512-mA resolution. Upon POR, default discharge current limit is 6.144 A on 10-mΩ current sensing resistor (RSR).

To provide secondary protection during battery discharge, the bq24780S has an ILIM pin with which the user can program the maximum discharge current. Typically, the user sets the limit below battery pack over current protection (OCP) threshold for maximum battery discharge capacity. Refer to battery specification for OCP information. Internal discharge current limit is the lower one between the voltage set by DischargeCurrent(), and the voltage on ILIM pin. To disable this function, the user can pull ILIM pin above 1.6V, which is the maximum discharge current regulation limit. When ILIM is below 60mV, battery discharge is disabled. The preferred discharge current limit can be derived from Equation 5.

Equation 5. bq24780S eq_Idchg_SLUSBW0.gif

Table 15. Discharge Current Register (0x39H), Using 10-mΩ Sense Resistor

BITBIT NAMEDESCRIPTION
0Not used; value ignored
1Not used; value ignored
2Not used; value ignored
3Not used; value ignored
4Not used; value ignored
5Not used; value ignored
6Not used; value ignored
7Not used; value ignored
8Not used; value ignored
9Discharge current, DACIIN 00 = Adds 0 mA of input current
1 = Adds 512 mA of discharge current
10Discharge current, DACIIN 10 = Adds 0 mA of input current
1 = Adds 1024 mA of discharge current
11Discharge current, DACIIN 20 = Adds 0 mA of input current
1 = Adds 2048 mA of discharge current
12Discharge current, DACIIN 30 = Adds 0 mA of input current
1 = Adds 4096 mA of discharge current
13Discharge current, DACIIN 40 = Adds 0 mA of input current
1 = Adds 8192 mA of discharge current
14Discharge current, DACIIN 50 = Adds 0 mA of input current
1 = Adds 16384 mA of discharge current
15Not used; 1 = invalid write