JAJSFE4B May   2015  – May 2018

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      概略回路図
  4. 改訂履歴
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current
    6. 7.6  Digital Input and Output DC Characteristics
    7. 7.7  Power-On Reset
    8. 7.8  2.5-V LDO Regulator
    9. 7.9  Internal Clock Oscillators
    10. 7.10 Integrating ADC (Coulomb Counter) Characteristics
    11. 7.11 ADC (Temperature and Cell Voltage) Characteristics
    12. 7.12 Data Flash Memory Characteristics
    13. 7.13 HDQ Communication Timing Characteristics
    14. 7.14 I2C-Compatible Interface Timing Characteristics
    15. 7.15 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fuel Gauging
      2. 8.3.2 Impedance Track Variables
      3. 8.3.3 Power Control
        1. 8.3.3.1 Reset Functions
        2. 8.3.3.2 Wake-Up Comparator
        3. 8.3.3.3 Flash Updates
      4. 8.3.4 Autocalibration
      5. 8.3.5 Communications
        1. 8.3.5.1 Authentication
        2. 8.3.5.2 Key Programming (Data Flash Key)
        3. 8.3.5.3 Key Programming (Secure Memory Key)
        4. 8.3.5.4 Executing an Authentication Query
        5. 8.3.5.5 HDQ Single-Pin Serial Interface
        6. 8.3.5.6 HDQ Host Interruption Feature
          1. 8.3.5.6.1 Low Battery Capacity
          2. 8.3.5.6.2 Temperature
        7. 8.3.5.7 I2C Interface
          1. 8.3.5.7.1 I2C Time Out
          2. 8.3.5.7.2 I2C Command Waiting Time
          3. 8.3.5.7.3 I2C Clock Stretching
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
        1. 8.4.1.1 NORMAL Mode
        2. 8.4.1.2 SLEEP Mode
        3. 8.4.1.3 FULLSLEEP Mode
        4. 8.4.1.4 HIBERNATE Mode
      2. 8.4.2 System Control Function
        1. 8.4.2.1 SHUTDOWN Mode
        2. 8.4.2.2 INTERRUPT Mode
      3. 8.4.3 Security Modes
        1. 8.4.3.1 Sealing and Unsealing Data Flash
    5. 8.5 Programming
      1. 8.5.1 Standard Data Commands
        1. 8.5.1.1 Control(): 0x00 and 0x01
    6. 8.6 Register Maps
      1. 8.6.1 Pack Configuration Register
      2. 8.6.2 Pack Configuration B Register
      3. 8.6.3 Pack Configuration C Register
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 BAT Voltage Sense Input
        2. 9.2.2.2 SRP and SRN Current Sense Inputs
        3. 9.2.2.3 Sense Resistor Selection
        4. 9.2.2.4 TS Temperature Sense Input
        5. 9.2.2.5 Thermistor Selection
        6. 9.2.2.6 REGIN Power Supply Input Filtering
        7. 9.2.2.7 VCC LDO Output Filtering
    3. 9.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Sense Resistor Connections
      2. 11.1.2 Thermistor Connections
      3. 11.1.3 High-Current and Low-Current Path Separation
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

I2C Clock Stretching

I2C clock stretches can occur during all modes of fuel gauge operation. In the SLEEP and HIBERNATE modes, a short clock stretch will occur on all I2C traffic as the device must wake-up to process the packet. In NORMAL and SLEEP modes, clock stretching will only occur for packets addressed for the fuel gauge. The timing of stretches will vary as interactions between the communicating host and the gauge are asynchronous. The I2C clock stretches may occur after start bits, the ACK/NAK bit, and first data bit transmit on a host read cycle. The majority of clock stretch periods are small (≤ 4 ms) as the I2C interface peripheral and CPU firmware perform normal data flow control. However, less frequent but more significant clock stretch periods may occur when data flash (DF) is being written by the CPU to update the resistance (Ra) tables and other DF parameters, such as Qmax. Due to the organization of DF, updates need to be written in data blocks consisting of multiple data bytes.

An Ra table update requires erasing a single page of DF, programming the updated Ra table and a flag. The potential I2C clock stretching time is 24-ms max. This includes 20-ms page erase and 2-ms row programming time (×2 rows). The Ra table updates occur during the discharge cycle and at up to 15 resistance grid points that occur during the discharge cycle.

A DF block write typically requires a max of 72 ms. This includes copying data to a temporary buffer and updating DF. This temporary buffer mechanism is used for protection from power failure during a DF update. The first part of the update requires 20 ms time to erase the copy buffer page, 6 ms to write the data into the copy buffer, and the program progress indicator (2 ms for each individual write). The second part of the update is writing to the DF and requires 44-ms DF block update time. This includes a 20-ms each page erase for two pages and a 2-ms each row write for two rows.

In the event that a previous DF write was interrupted by a power failure or reset during the DF write, an additional 44-ms max DF restore time is required to recover the data from a previously interrupted DF write. In this power failure recovery case, the total I2C clock stretching is 116-ms max.

Another case where I2C clock stretches is at the end of discharge. The update to the last discharge data will go through the DF block update twice because two pages are used for the data storage. The clock stretching in this case is 144-ms max. This occurs if there has been a Ra table update during the discharge.