JAJSDZ7B March   2016  – October 2017

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Supply Current
    6. 6.6  Electrical Characteristics: Power Supply Control
    7. 6.7  Electrical Characteristics: AFE Power-On Reset
    8. 6.8  Electrical Characteristics: AFE Watchdog Reset and Wake Timer
    9. 6.9  Electrical Characteristics: Current Wake Comparator
    10. 6.10 Electrical Characteristics: VC1, VC2, VC3, VC4, BAT, PACK
    11. 6.11 Electrical Characteristics: SMBD, SMBC
    12. 6.12 Electrical Characteristics: PRES, BTP_INT, DISP
    13. 6.13 Electrical Characteristics: LEDCNTLA, LEDCNTLB, LEDCNTLC
    14. 6.14 Electrical Characteristics: Coulomb Counter
    15. 6.15 Electrical Characteristics: CC Digital Filter
    16. 6.16 Electrical Characteristics: ADC
    17. 6.17 Electrical Characteristics: ADC Digital Filter
    18. 6.18 Electrical Characteristics: CHG, DSG FET Drive
    19. 6.19 Electrical Characteristics: PCHG FET Drive
    20. 6.20 Electrical Characteristics: FUSE Drive
    21. 6.21 Electrical Characteristics: Internal Temperature Sensor
    22. 6.22 Electrical Characteristics: TS1, TS2, TS3, TS4
    23. 6.23 Electrical Characteristics: PTC, PTCEN
    24. 6.24 Electrical Characteristics: Internal 1.8-V LDO
    25. 6.25 Electrical Characteristics: High-Frequency Oscillator
    26. 6.26 Electrical Characteristics: Low-Frequency Oscillator
    27. 6.27 Electrical Characteristics: Voltage Reference 1
    28. 6.28 Electrical Characteristics: Voltage Reference 2
    29. 6.29 Electrical Characteristics: Instruction Flash
    30. 6.30 Electrical Characteristics: Data Flash
    31. 6.31 Electrical Characteristics: OCD, SCC, SCD1, SCD2 Current Protection Thresholds
    32. 6.32 Timing Requirements: OCD, SCC, SCD1, SCD2 Current Protection Timing
    33. 6.33 Timing Requirements: SMBus
    34. 6.34 Timing Requirements: SMBus XL
    35. 6.35 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Primary (1st Level) Safety Features
      2. 7.3.2  Secondary (2nd Level) Safety Features
      3. 7.3.3  Charge Control Features
      4. 7.3.4  Gas Gauging
      5. 7.3.5  Configuration
        1. 7.3.5.1 Oscillator Function
        2. 7.3.5.2 System Present Operation
        3. 7.3.5.3 Emergency Shutdown
        4. 7.3.5.4 1-Series, 2-Series, 3-Series, or 4-Series Cell Configuration
        5. 7.3.5.5 Cell Balancing
      6. 7.3.6  Battery Parameter Measurements
        1. 7.3.6.1 Charge and Discharge Counting
      7. 7.3.7  Battery Trip Point (BTP)
      8. 7.3.8  Lifetime Data Logging Features
      9. 7.3.9  Authentication
      10. 7.3.10 LED Display
      11. 7.3.11 Voltage
      12. 7.3.12 Current
      13. 7.3.13 Temperature
      14. 7.3.14 Communications
        1. 7.3.14.1 SMBus On and Off State
        2. 7.3.14.2 SBS Commands
    4. 7.4 Device Functional Modes
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 High-Current Path
          1. 8.2.2.1.1 Protection FETs
          2. 8.2.2.1.2 Chemical Fuse
          3. 8.2.2.1.3 Lithium-Ion Cell Connections
          4. 8.2.2.1.4 Sense Resistor
          5. 8.2.2.1.5 ESD Mitigation
        2. 8.2.2.2 Gas Gauge Circuit
          1. 8.2.2.2.1 Coulomb-Counting Interface
          2. 8.2.2.2.2 Power Supply Decoupling and PBI
          3. 8.2.2.2.3 System Present
          4. 8.2.2.2.4 SMBus Communication
          5. 8.2.2.2.5 FUSE Circuitry
        3. 8.2.2.3 Secondary-Current Protection
          1. 8.2.2.3.1 Cell and Battery Inputs
          2. 8.2.2.3.2 External Cell Balancing
          3. 8.2.2.3.3 PACK and FET Control
          4. 8.2.2.3.4 Temperature Output
          5. 8.2.2.3.5 LEDs
          6. 8.2.2.3.6 Safety PTC Thermistor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors
      2. 10.1.2 ESD Spark Gap
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

RSM Package
32-Pin VQFN with Exposed Thermal Pad
Top View

Pin Functions

PIN TYPE DESCRIPTION
NAME NUMBER
PBI 1 P(1) Power supply backup input pin
VC4 2 IA Sense voltage input pin for the most positive cell, and balance current input for the most positive cell
VC3 3 IA Sense voltage input pin for the second most positive cell, balance current input for the second most positive cell, and return balance current for the most positive cell
VC2 4 IA Sense voltage input pin for the third most positive cell, balance current input for the third most positive cell, and return balance current for the second most positive cell
VC1 5 IA Sense voltage input pin for the least positive cell, balance current input for the least positive cell, and return balance current for the third most positive cell
SRN 6 I Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN where SRP is the top of the sense resistor.
NC 7 — Not internally connected. Connect to VSS.
SRP 8 I Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN where SRP is the top of the sense resistor.
VSS 9 P Device ground
TS1 10 IA Temperature sensor 1 thermistor input pin
TS2 11 IA Temperature sensor 2 thermistor input pin
TS3 12 IA Temperature sensor 3 thermistor input pin
TS4 13 IA Temperature sensor 4 thermistor input pin
NC 14 — Not internally connected. Connect to VSS.
BTP_INT 15 O Battery Trip Point (BTP) interrupt output
PRES or SHUTDN 16 I Host system present input for removable battery pack or emergency system shutdown input for embedded packs
DISP 17 — Display control for LEDs
SMBD 18 I/OD SMBus data pin
SMBC 19 I/OD SMBus clock pin
LEDCNTLA 20 — LED display segment that drives the external LEDs depending on the firmware configuration
LEDCNTLB 21 — LED display segment that drives the external LEDs depending on the firmware configuration
LEDCNTLC 22 — LED display segment that drives the external LEDs depending on the firmware configuration
PTC 23 IA Safety PTC thermistor input pin. To disable, connect PTC and PTCEN to VSS.
PTCEN 24 IA Safety PTC thermistor enable input pin. Connect to BAT. To disable, connect PTC and PTCEN to VSS.
FUSE 25 O Fuse drive output pin
VCC 26 P Secondary power supply input
PACK 27 IA Pack sense input pin
DSG 28 O NMOS Discharge FET drive output pin
NC 29 — Not internally connected. Connect to VSS.
PCHG 30 O PMOS Precharge FET drive output pin
CHG 31 O NMOS Charge FET drive output pin
BAT 32 P Primary power supply input pin
(1) P = Power Connection, O = Digital Output, AI = Analog Input, I = Digital Input, I/OD = Digital Input/Output
bq4050 IO_1.gif Figure 1. Pin Equivalent Diagram 1
bq4050 IO_2.gif Figure 2. Pin Equivalent Diagram 2
bq4050 IO_3.gif Figure 3. Pin Equivalent Diagram 3