JAJSD34C April   2017  – April 2018 CSD88599Q5DC

PRODUCTION DATA.  

  1. 1特長
  2. 2アプリケーション
  3. 3概要
  4. 4改訂履歴
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Power Block Performance
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Power Block Device Characteristics
    7. 5.7 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Brushless DC Motor With Trapezoidal Control
    3. 6.3 Power Loss Curves
    4. 6.4 Safe Operating Area (SOA) Curve
    5. 6.5 Normalized Power Loss Curves
    6. 6.6 Design Example – Regulate Current to Maintain Safe Operation
    7. 6.7 Design Example – Regulate Board and Case Temperature to Maintain Safe Operation
      1. 6.7.1 Operating Conditions
      2. 6.7.2 Calculating Power Loss
      3. 6.7.3 Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Layout Guidelines
      1. 7.1.1 Electrical Performance
      2. 7.1.2 Thermal Considerations
    2. 7.2 Layout Example
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 コミュニティ・リソース
    3. 8.3 商標
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 Glossary
  9. 9メカニカル、パッケージ、および注文情報
    1. 9.1 Q5DCパッケージの寸法
    2. 9.2 推奨ランド・パターン
    3. 9.3 推奨ステンシル

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DMM|22
サーマルパッド・メカニカル・データ
発注情報

6.3 Power Loss Curves

CSD88599Q5DC was designed to operate up to 10-cell Li-Ion battery voltage applications ranging from 30 V to 42 V, typical 36 V. For 11 and 12s, input voltages between 42 V to 54 V, RC snubbers are required for each switch-node U, V, and W. To reduce ringing, refer to the Electrical Performance section. In an effort to simplify the design process, Texas Instruments has provided measured power loss performance curves over a variety of typical conditions.

Figure 1 plots the CSD88599Q5DC power loss as a function of load current. The measured power loss includes both input conversion loss and gate drive loss.

Equation 1 is used to generate the power loss curve:

Equation 1. Power loss (W) = (VIN × IIN_SHUNT) + (VDD × IDD_SHUNT) – (VSW_AVG × IOUT)

The power loss measurements were made on the circuit shown in Figure 19. Power block devices for legs U and V, PB1 and PB2 were disabled by shorting the CSD88599Q5DC high-side and low-side FETs' gate-to-source terminals. Current shunt Iin_SHUNT provides input current and Idd_SHUNT provides driver supply current measurements. The winding current is measured from the DC load. An averaging circuit provides switch node W equivalent RMS voltage.

CSD88599Q5DC Pwr_Loss_Test_Ckt.gifFigure 19. Power Loss Test Circuit

The RMS current on the CSD88599Q5DC device depends on the motor winding current. For trapezoidal control, the MOSFET RMS current is calculated using Equation 2.

Equation 2. IRMS = IOUT × √2

Taking into consideration system tolerances with the current measurement scheme, the inverter design needs to withstand a 20% overload current.

Table 1. RMS and Overload Current Calculations

Winding RMS Current (A) CSD88599Q5DC IRMS (A) Overload 20% × IRMS (A)
20 28 34
30 42 51
40 56 68