JAJSDO4B February   2017  – August 2017 DAC38RF82 , DAC38RF89

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
  4. 改訂履歴
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - DC Specifications
    6. 7.6  Electrical Characteristics - Digital Specifications
    7. 7.7  Electrical Characteristics - AC Specifications
    8. 7.8  PLL/VCO Electrical Characteristics
    9. 7.9  Timing Requirements
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  SerDes Inputs
      2. 8.3.2  SerDes Rate
      3. 8.3.3  SerDes PLL
      4. 8.3.4  SerDes Equalizer
      5. 8.3.5  JESD204B Descrambler
      6. 8.3.6  JESD204B Frame Assembly
      7. 8.3.7  SYNC Interface
      8. 8.3.8  Single or Dual Link Configuration
      9. 8.3.9  Multi-Device Synchronization
      10. 8.3.10 SYSREF Capture Circuit
      11. 8.3.11 JESD204B Subclass 0 Support
      12. 8.3.12 SerDes Test Modes through Serial Programming
      13. 8.3.13 SerDes Test Modes through IEEE 1500 Programming
      14. 8.3.14 Error Counter
      15. 8.3.15 Eye Scan
      16. 8.3.16 JESD204B Pattern Test
      17. 8.3.17 Wideband DUC (wide-DUC)
      18. 8.3.18 Interpolation Block
        1. 8.3.18.1 Multi-DUC input
        2. 8.3.18.2 Interpolation Filters
        3. 8.3.18.3 JESD204B Modes, Interpolation and Clock phase Programming
        4. 8.3.18.4 Inverse Sinc Filter
      19. 8.3.19 PA Protection Block
      20. 8.3.20 Gain Block
      21. 8.3.21 Output Summation
      22. 8.3.22 Output Delay
      23. 8.3.23 Polarity Inversion
      24. 8.3.24 Temperature Sensor
      25. 8.3.25 Alarm Monitoring
      26. 8.3.26 Differential Clock Inputs
      27. 8.3.27 CMOS Digital Inputs
      28. 8.3.28 DAC Fullscale Output Current
      29. 8.3.29 Current Steering DAC Architecture
      30. 8.3.30 DAC Transfer Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 Clocking Modes
      2. 8.4.2 PLL Bypass Mode Programming
      3. 8.4.3 Internal PLL/VCO
      4. 8.4.4 CLKOUT
      5. 8.4.5 Serial Peripheral Interface (SPI)
        1. 8.4.5.1 NORMAL (RW)
        2. 8.4.5.2 WRITE_TO_CLEAR (W0C)
    5. 8.5 Register Maps
      1. 8.5.1  Chip Reset and Configuration Register (address = 0x00) [reset = 0x5803]
      2. 8.5.2  IO Configuration Register (address = 0x01) [reset = 0x1800]
      3. 8.5.3  Lane Single Detect Alarm Mask Register (address = 0x02) [reset = 0xFFFF]
      4. 8.5.4  Clock Alarms Mask Register (address = 0x03) [reset = 0xFFFF
      5. 8.5.5  SERDES Loss of Signal Detection Alarms Register (address = 0x04) [reset = 0x0000]
      6. 8.5.6  SYSREF Alignment Circuit Alarms Register (address = 0x05) [reset = 0x0000]
      7. 8.5.7  Temperature Sensor and PLL Loop Voltage Register (address = 0x06) [reset = variable]
      8. 8.5.8  Page Set Register (address = 0x09) [reset = 0x0000]
      9. 8.5.9  SYSREF Align to r1 and r3 Count Register (address = 0x78) [reset = 0x0000]
      10. 8.5.10 SYSREF Phase Count 1 and 2 Register (address = 0x79) [reset = 0x0000]
      11. 8.5.11 SYSREF Phase Count 3 and 4 Register (address = 0x7A) [reset = 0x0000]
      12. 8.5.12 Vendor ID and Chip Version Register (address = 0x7F) [reset = 0x0008]]
      13. 8.5.13 Multi-DUC Configuration (PAP, Interpolation) Register (address = 0x0A) [reset = 0x02B0]
      14. 8.5.14 Multi-DUC Configuration (Mixers) Register (address = 0x0C) [reset = 0x2402]
      15. 8.5.15 JESD FIFO Control Register (address = 0x0D) [reset = 0x1300]
      16. 8.5.16 Alarm Mask 1 Register (address = 0x0E) [reset = 0x00FF]
      17. 8.5.17 Alarm Mask 2 Register (address = 0x0F) [reset = 0xFFFF]
      18. 8.5.18 Alarm Mask 3 Register (address = 0x10) [reset = 0xFFFF]
      19. 8.5.19 Alarm Mask 4 Register (address = 0x11) [reset = 0xFFFF]
      20. 8.5.20 JESD Lane Skew Register (address = 0x12) [reset = 0x0000]
      21. 8.5.21 CMIX Configuration Register (address = 0x17) [reset = 0x0000]
      22. 8.5.22 Output Summation and Delay Register (address = 0x19) [reset = 0x0000]
      23. 8.5.23 NCO Phase Path AB Register (address = 0x1C) [reset = 0x0000]
      24. 8.5.24 NCO Phase Path CD Register (address = 0x1D) [reset = 0x0000]
      25. 8.5.25 NCO Frequency Path AB Register (address = 0x1E-0x20) [reset = 0x0000 0000 0000]
      26. 8.5.26 NCO Frequency Path CD Register (address = 0x21-0x23) [reset = 0x0000 0000 0000]
      27. 8.5.27 SYSREF Use for Clock Divider Register (address = 0x24) [reset = 0x0010]
      28. 8.5.28 Serdes Clock Control Register (address = 0x25) [reset = 0x7700]
      29. 8.5.29 Sync Source Control 1 Register (address = 0x27) [reset = 0x1144]
      30. 8.5.30 Sync Source Control 2 Register (address = 0x28) [reset = 0x0000]
      31. 8.5.31 PAP path AB Gain Attenuation Step Register (address = 0x29) [reset = 0x0000]
      32. 8.5.32 PAP path AB Wait Time Register (address = 0x2A) [reset = 0x0000]
      33. 8.5.33 PAP path CD Gain Attenuation Step Register (address = 0x2B) [reset = 0x0000]
      34. 8.5.34 PAP Path CD Wait Time Register (address = 0x2C) [reset = 0x0000]
      35. 8.5.35 PAP path AB Configuration Register (address = 0x2D) [reset = 0x0FFF]
      36. 8.5.36 PAP path CD Configuration Register (address = 0x2E) [reset = 0x0FFF]
      37. 8.5.37 DAC SPI Configuration Register (address = 0x2F) [reset = 0x0000]
      38. 8.5.38 DAC SPI Constant Register (address = 0x30) [reset = 0x0000]
      39. 8.5.39 Gain for path AB Register (address = 0x32) [reset = 0x0000]
      40. 8.5.40 Gain for path CD Register (address = 0x33) [reset = 0x0000]
      41. 8.5.41 JESD Error Counter Register (address = 0x41) [reset = 0x0000]
      42. 8.5.42 JESD ID 1 Register (address = 0x46) [reset = 0x0044]
      43. 8.5.43 JESD ID 2 Register (address = 0x47) [reset = 0x190A]
      44. 8.5.44 JESD ID 3 and Subclass Register (address = 0x48) [reset = 0x31C3]
      45. 8.5.45 JESD Lane Enable Register (address = 0x4A) [reset = 0x0003]
      46. 8.5.46 JESD RBD Buffer and Frame Octets Register (address = 0x4B) [reset = 0x1300]
      47. 8.5.47 JESD K and L Parameters Register (address = 0x4C) [reset = 0x1303]
      48. 8.5.48 JESD M and S Parameters Register (address = 0x4D) [reset = 0x0100]
      49. 8.5.49 JESD N, HD and SCR Parameters Register (address = 0x4E) [reset = 0x0F4F]
      50. 8.5.50 JESD Character Match and Other Register (address = 0x4F) [reset = 0x1CC1]
      51. 8.5.51 JESD Link Configuration Data Register (address = 0x50) [reset = 0x0000]
      52. 8.5.52 JESD Sync Request Register (address = 0x51) [reset = 0x00FF]
      53. 8.5.53 JESD Error Output Register (address = 0x52) [reset = 0x00FF]
      54. 8.5.54 JESD ILA Check 1 Register (address = 0x53) [reset = 0x0100]
      55. 8.5.55 JESD ILA Check 2 Register (address = 0x54) [reset = 0x8E60]
      56. 8.5.56 JESD SYSREF Mode Register (address = 0x5C) [reset = 0x0001]
      57. 8.5.57 JESD Crossbar Configuration 1 Register (address = 0x5F) [reset = 0x0123]
      58. 8.5.58 JESD Crossbar Configuration 2 Register (address = 0x60) [reset = 0x4567]
      59. 8.5.59 JESD Alarms for Lane 0 Register (address = 0x64) [reset = 0x0000]
      60. 8.5.60 JESD Alarms for Lane 1 Register (address = 0x65 01100101) [reset = 0x0000]
      61. 8.5.61 JESD Alarms for Lane 2 Register (address = 0x66) [reset = 0x0000]
      62. 8.5.62 JESD Alarms for Lane 3 Register (address = 0x67) [reset = 0x0000]
      63. 8.5.63 JESD Alarms for Lane 4 Register (address = 0x68) [reset = 0x0000]
      64. 8.5.64 JESD Alarms for Lane 5 Register (address = 0x69) [reset = 0x0000]
      65. 8.5.65 JESD Alarms for Lane 6 Register (address = 0x6A [reset = 0x0000]
      66. 8.5.66 JESD Alarms for Lane 7 Register (address = 0x6B) [reset = 0x0000]
      67. 8.5.67 SYSREF and PAP Alarms Register (address = 0x6C) [reset = 0x0000]
      68. 8.5.68 Clock Divider Alarms 1 Register (address = 0x6D) [reset = 0x0000]
      69. 8.5.69 Clock Configuration Register (address = 0x0A) [reset = 0xF000]
      70. 8.5.70 Sleep Configuration Register (address = 0x0B) [reset = 0x0022]
      71. 8.5.71 Divided Output Clock Configuration Register (address = 0x0C) [reset = 0x8000]
      72. 8.5.72 DAC Fullscale Current Register (address = 0x0D) [reset = 0xF000]
      73. 8.5.73 Internal SYSREF Generator Register (address = 0x10) [reset = 0x0000]
      74. 8.5.74 Counter for Internal SYSREF Generator Register (address = 0x11) [reset = 0x0000]
      75. 8.5.75 SPI SYSREF for Internal SYSREF Generator Register (address = 0x12) [reset = 0x0000]
      76. 8.5.76 Digital Test Signals Register (address = 0x1B) [reset = 0x0000]
      77. 8.5.77 Sleep Pin Control Register (address = 0x23) [reset = 0xFFFF]
      78. 8.5.78 SYSREF Capture Circuit Control Register (address = 0x24) [reset = 0x1000]
      79. 8.5.79 Clock Input and PLL Configuration Register (address = 0x31) [reset = 0x0200]
      80. 8.5.80 PLL Configuration 1 Register (address = 0x32) [reset = 0x0308]
      81. 8.5.81 PLL Configuration 2 Register (address = 0x33) [reset = 0x4018]
      82. 8.5.82 LVDS Output Configuration Register (address = 0x34) [reset = 0x0000]
      83. 8.5.83 Fuse Farm clock divider Register (address = 0x35) [reset = 0x0018]
      84. 8.5.84 Serdes Clock Configuration Register (address = 0x3B) [reset = 0x0002]
      85. 8.5.85 Serdes PLL Configuration Register (address = 0x3C) [reset = 0x8228]
      86. 8.5.86 Serdes Configuration 1 Register (address = 0x3D) [reset = 0x0x0088]
      87. 8.5.87 Serdes Configuration 2 Register (address = 0x3E) [reset = 0x0x0909]
      88. 8.5.88 Serdes Polarity Control Register (address = 0x3F) [reset = 0x0000]
      89. 8.5.89 JESD204B SYNCB OUTPUT Register (address = 0x76) [reset = 0x0000]
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Start-up Sequence
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Calculating the JESD204B SerDes rate
      4. 9.2.4 Calculating valid JESD204B SYSREF Frequency
      5. 9.2.5 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 関連リンク
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

特長

  • マルチモード動作の14ビット分解能、9GSPSのDAC
    • 16ビット、デュアル・チャネルのデータ・モード
      • 最大入力速度: 2.5GSPS
      • 広帯域のデジタル・アップコンバータ
        • 補間: 1、2、4、6、8、10、12、16、18、20、24x
    • 12ビット、デュアル・チャネルのデータ・モード
      • 最大入力速度: 3.33GSPS
      • 広帯域のデジタル・アップコンバータ
        • 補間: 1、2、24x
    • 8ビット、シングル・チャネルのデータ・モード
      • 最大入力速度: 9GSPS
  • JESD204Bインターフェイス
    • サブクラス1のマルチチップ同期
    • 最大レーン速度: 12.5Gbps
  • 差動出力
    • DCカップリングをサポート
    • RFフルスケール出力電力(2:1バランの場合):
      2.14GHzで3dBm
  • PLLおよびVCO内蔵、バイパス付き
    • DAC38RF82: fC(VCO) = 5.9または8.9GHz
    • DAC38RF89: fC(VCO) = 5または7.5GHz
  • 電源電圧: -1.8V、1.0V、1.8V
  • パッケージ: 10×10mm BGA、0.8mmピッチ、
    144ボール

アプリケーション

  • 任意波形の生成器
  • レーダーおよび電子兵器
  • 通信テスト機器
  • DOCSIS 3.0/3.1用の直接RF合成
  • マイクロ波バックホール

概要

DAC38RF82およびDAC38RF89は高性能、広帯域幅のRFサンプリング・デジタル/アナログ・コンバータ(DAC)で、デュアル・チャネルで3.33GSPSまで、8ビットのシングル・チャネルで9GSPSまでの入力データに対応できます。これらのデバイスは低消費電力のJESD204Bインターフェイスを持ち、最大8レーンで12.5Gbpsまでのビット速度をサポートします。

デュアル・チャネル動作では、入力インターフェイスは12ビット分解能で3.33GSPS、16ビット分解能で2.5GSPSまでのデータ速度に、補間なしで対応できます。2xから24xまでの補間モードを使用する、複雑なベースバンド送信機として使用するとき、DAC38RF82またはDAC38RF89は16ビット入力分解能で2GHz、12ビット入力分解能で2.66GHzまでの広い帯域幅の信号を合成できます。

8ビット・モードでは最大9GSPSのDACサンプル速度での入力に対応し、0~4.5GHzの広い帯域幅の信号を合成できます。

オプションの低ジッタPLL/VCOにより、低い周波数の基準クロックを使用できるため、DACクロックの生成が簡単になります。DAC38RF82およびDAC38RF89は、「デバイス比較表」に要約されているように、それぞれ異なるVCO周波数範囲に対応しています。

製品情報(1)

型番 パッケージ 本体サイズ(公称)
DAC38RF82 FCBGA (144) 10.0mm×10.0mm
DAC38RF89
  1. 利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。

32×6MHz、256QAMの搬送波

DAC38RF82 DAC38RF89 192MHz_QAM_SLASEA6.gif

改訂履歴

Changes from A Revision (April 2017) to B Revision

  • Deleted 「特長」の「補間: 1、2、4、24x」を「補間: 1、2、24x」に変更し、「4」をGo
  • Changed the ALARM pin From: alarm_out_pol To: alm_out_pol in the Pin Functions tableGo
  • Changed the Description of pins A3, A4, A7, A6, A9, A10, A12, E12, F11, F7, G6, H5, H7, J6, J11 in the Pin Functions tableGo
  • Changed description of TXENABLE pin in the PIN Functions tableGo
  • Changed the MAX value of VEE18N rail From: 0.5 V To 0.3 V in the Absolute Maximum Ratings tableGo
  • Added "Supply Voltage Range" to the Recommended Operating Conditions tableGo
  • Changed DNL typical value From: ±0.5 to ±3 LSB in Electrical Characteristics - DC Specifications tableGo
  • Changed INL typical value From: ±1 To: ±4 LSB in Electrical Characteristics - DC Specifications tableGo
  • Added "Reference voltage drift" to the Electrical Characteristics - DC Specifications tableGo
  • Changed Power Dissipation Test Condition From: MODE 5: dual channel, 8-bit input mode, 2x Interpolation To: MODE 5: dual channel, 8-bit input mode, 1x Interpolation in the Electrical Characteristics - DC SpecificationsGo
  • Changed the ILOAD values to negative for CMOS interface parameter, low-level output voltage, in the Electrical Characteristics - Digital Specifications tableGo
  • Added 0 dBFS to the condition statement for the Electrical Characteristics - AC Specifications tableGo
  • Added MIN and TYP value to maximum DAC sample rate for DAC38RF89 only in the Electrical Characteristics - AC Specifications tableGo
  • Changed the Isolation values in the TEST CONDITIONS, TYP value From: 74 dBc To: 82 dBc and 56 dBc To 73 dBc in the Electrical Characteristics - AC Specifications tableGo
  • Added NSD values for DAC38RF82 with on-chip PLL enabled to Electrical Characteristics - AC Specifications tableGo
  • Added Figure 16Go
  • Changed the MPY values in Table 4Go
  • Added MPY value for 16.5x in the Table 4Go
  • Changed input rate max and fdac max for 6x interpolation mode in Table 9 Go
  • Changed input data rate From: 6666 MSPS To: 3333 MSPS for LMFSHd=41380, 2x interpolation in Table 9 Go
  • Changed Table 12, JESD204B frame format for LMFSHd=84111 Go
  • Changed Table 14, JESD204B frame format for LMFSHd=44210Go
  • Changed Table 16, JESD204B frame format for LMFSHd = 24410Go
  • Changed Table 17, JESD204B frame format for LMFSHd = 44210Go
  • Changed Table 18, JESD204B frame format for LMFSHd = 88210Go
  • Changed Table 19, JESD204B frame format for LMFSHd = 24410Go
  • Changed Table 20, JESD204B frame format for LMFSHd=48410Go
  • Changed Table 21, JESD204B frame format for LMFSHd = 24310Go
  • Changed Table 22, JESD204B frame format for LMFSHd = 48310Go
  • Changed Table 23, JESD204B frame format for LMFSHd = 81180Go
  • Changed Table 24, JESD204B frame format for LMFSHd = 41380Go
  • Changed Table 26, JESD204B frame format for LMFSHd = 41121Go
  • Added Table 27, JESD204B frame format for LMFSHd = 41121Go
  • Changed Table 38Go
  • Changed register field programming values for LMFSHd=24410, 41380, 41121 and 24310 in the Register Programming for JESD and Interpolation Mode tableGo
  • Changed the bit positions of N_M1 register field From: 12-8 To: 4-0 in the Table 42 tableGo
  • Changed the bit positions of N_M1’ (NPRIME_M1) register field From: 4-0 To: 12-0 in the Table 42 tableGo
  • Deleted ISFIRCD_ENA and ISFIRAB _ENA regsiter fields. Added ISFIR_ENA register field in Inverse Sinc FilterGo
  • Changed the description of DAC PLL alarm in Alarm MonitoringGo
  • Changed from BIST_ENA to Reserved in Table 61 Go
  • Changed from BIST_ZERO to Reserved in Table 61 Go
  • Changed the description of OUTSUM_SEL field in Table 69 Go
  • Changed the junction temp and loop filter voltage range for PLL tuning in Figure 141Go

Changes from * Revision (February 2017) to A Revision