7.4.4 SPI Interfaced FOUNDATION FIELDBUS / PROFIBUS PA

FOUNDATION FIELDBUS and PROFIBUS PA are half-duplex communication protocols where only the encoder or decoder are active at any time and the DAC8742H arbitrates over which path is active. When interfacing the FOUNDATION FIELDBUS or PROFIBUS PA encoder via SPI interface, data is placed in transmit and receive FIFOs that are each 16-bytes deep to buffer all data.

When receiving data the decoder will expect a preamble byte(s) and a start delimiter byte, followed by the data bytes for the packet, and concluded with a stop delimiter byte. All of these bytes are placed into the RECEIVE FIFO where bits 7:0 represent the data and bit 8 is used as a special bit to indicate the start of a packet, with data 0x014D, the end of a packet, with data 0x0126, or a half-bit slip, with data 0x0100. If a half-bit slip occurs it is recommended to discard the packet. A timer is not necessary to detect the end of receiving a packet in SPI mode because the stop delimiter is included in the RECEIVE FIFO data.

In order to prevent RECEIVE FIFO overflow, alarms are available to watch a threshold of the FIFO or when the FIFO is full. If the FIFO is full it is possible for data to be lost. This is achieved by programming the FIFO LEVEL SET register (bits 7:4) to the desired threshold value from 1-15, if a full FIFO (level 16 threshold) is desired the M2D FIFO FULL alarm can be used instead. If the M2D FIFO LEVEL bit (bit 7) in the MODEM IRQ MASK register is set to 0, the IRQ pin will toggle and the MODEM STATUS register should be read to determine the source of the interrupt. Receive data can then be read from the RECEIVE FIFO by issuing an SPI read command.

The encoder will begin to send data by sending the preamble byte(s) followed by a start delimiter when the TRANSMIT FIFO is not empty and the device is not receiving data. The number of preamble bytes used in the packet is controlled by the PAFF PREAMBLE bits (bits14:12) in the MODEM CONTROL REGISTER. The polarity of the Manchester encoded data can also be programmed by the PAFF POLARITY bit (bit 15) in the MODEM CONTROL REGISTER. After transmitting the preamble byte(s) and start delimiter the encoder will begin taking data from the TRANSMIT FIFO.

During transmission the SPI controller must take care to ensure that the TRANSMIT FIFO does not become empty before the packet is complete. When the TRANSMIT FIFO is empty a stop delimiter is placed on the bus.

The level of the transmit FIFO may be monitored in order to avoid buffer overflow. This can be done either by watching for a buffer full or buffer threshold event. To monitor by a FIFO level threshold the FIFO LEVEL SET register (bits 3:0) can be programmed to the desired threshold value from 1-15. If the D2M FIFO LEVEL bit (bit 4) in the MODEM IRQ MASK register is set to a 0, this will cause the IRQ pin to toggle. Similarly an alarm can be triggered based on the D2M FIFO FULL bit in the MODEM STATUS register.

The Jabber Inhibitor threshold can be programmed by the PAFF_JABBER register (address 0x27). The 8-bit value programmed in this register can be used to calculate the threshold using the equation below. When the timeout triggers the JAB_ON bit in the STATUS register will be taken high and transmission will be blocked for the 3 second timeout period. The JAB_OFF bit will go high when the timeout period has expired. Both JAB_ON and JAB_OFF bits trigger and IRQ event, meaning the IRQ pin will be triggered for both events.