JAJSCW9 February   2017 DAC8775

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Write and Readback Mode
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Current Output Stage
      2. 8.3.2  Voltage Output Stage
      3. 8.3.3  Buck-Boost Converter
        1. 8.3.3.1 Buck-Boost Converters Outputs
        2. 8.3.3.2 Selecting and Enabling Buck-Boost Converters
        3. 8.3.3.3 Configurable Clamp Feature and Current Output Settling Time
          1. 8.3.3.3.1 Default Mode - CCLP[1:0] = "00" - Current Output Only
          2. 8.3.3.3.2 Fixed Clamp Mode - CCLP[1:0] = "01" - Current and Voltage Output
          3. 8.3.3.3.3 Auto Learn Mode - CCLP[1:0] = "10" - Current Output Only
          4. 8.3.3.3.4 High Side Clamp (HSCLMP)
        4. 8.3.3.4 Buck-Boost Converters and Open Circuit Current Output
      4. 8.3.4  Analog Power Supply
      5. 8.3.5  Digital Power Supply
      6. 8.3.6  Internal Reference
      7. 8.3.7  Power-On-Reset
      8. 8.3.8  ALARM Pin
      9. 8.3.9  Power GOOD Bits
      10. 8.3.10 Status Register
      11. 8.3.11 Status Mask
      12. 8.3.12 Alarm Action
      13. 8.3.13 Watchdog Timer
      14. 8.3.14 Programmable Slew Rate
      15. 8.3.15 HART Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Peripheral Interface (SPI)
        1. 8.4.1.1 Stand-Alone Operation
        2. 8.4.1.2 Daisy-Chain Operation
      2. 8.4.2 SPI Shift Register
      3. 8.4.3 Write Operation
      4. 8.4.4 Read Operation
      5. 8.4.5 Updating the DAC Outputs and LDAC Pin
        1. 8.4.5.1 Asynchronous Mode
        2. 8.4.5.2 Synchronous Mode
      6. 8.4.6 Hardware RESET Pin
      7. 8.4.7 Hardware CLR Pin
      8. 8.4.8 Frame Error Checking
      9. 8.4.9 DAC Data Calibration
        1. 8.4.9.1 DAC Data Gain and Offset Calibration Registers
    5. 8.5 Register Maps
      1. 8.5.1 DAC8775 Commands
      2. 8.5.2 Register Maps and Bit Functions
        1. 8.5.2.1  No Operation Register (address = 0x00) [reset = 0x0000]
        2. 8.5.2.2  Reset Register (address = 0x01) [reset = 0x0000]
        3. 8.5.2.3  Reset Config Register (address = 0x02) [reset = 0x0000]
        4. 8.5.2.4  Select DAC Register (address = 0x03) [reset = 0x0000]
        5. 8.5.2.5  Configuration DAC Register (address = 0x04) [reset = 0x0000]
        6. 8.5.2.6  DAC Data Register (address = 0x05) [reset = 0x0000]
        7. 8.5.2.7  Select Buck-Boost Converter Register (address = 0x06) [reset = 0x0000]
        8. 8.5.2.8  Configuration Buck-Boost Register (address = 0x07) [reset = 0x0000]
        9. 8.5.2.9  DAC Channel Calibration Enable Register (address = 0x08) [reset = 0x0000]
        10. 8.5.2.10 DAC Channel Gain Calibration Register (address = 0x09) [reset = 0x0000]
        11. 8.5.2.11 DAC Channel Offset Calibration Register (address = 0x0A) [reset = 0x0000]
        12. 8.5.2.12 Status Register (address = 0x0B) [reset = 0x1000]
        13. 8.5.2.13 Status Mask Register (address = 0x0C) [reset = 0x0000]
        14. 8.5.2.14 Alarm Action Register (address = 0x0D) [reset = 0x0000]
        15. 8.5.2.15 User Alarm Code Register (address = 0x0E) [reset = 0x0000]
        16. 8.5.2.16 Reserved Register (address = 0x0F) [reset = N/A]
        17. 8.5.2.17 Write Watchdog Timer Register (address = 0x10) [reset = 0x0000]
        18. 8.5.2.18 Device ID Register (address = 0x11) [reset = 0x0000]
        19. 8.5.2.19 Reserved Register (address 0x12 - 0xFF) [reset = N/A]
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Buck-Boost Converter External Component Selection
      2. 9.1.2 Voltage and Current Ouputs on a Shared Terminal
      3. 9.1.3 Optimizing Current Output Settling time with Auto learn Mode
      4. 9.1.4 Protection for Industrial Transients
      5. 9.1.5 Implementing HART with DAC8775
    2. 9.2 Typical Application
      1. 9.2.1 1W Power Dissipation, Quad Channel, EMC and EMI Protected Analog Output Module with Adaptive Power Management
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Power Supply Recommendations

There are three possible hardware power supply configurations for the DAC8775: the internal DC/DC provides both positive and negative supply voltages, the internal DC/DC provides only one of the supply voltages with an external supply provided on the other, or the internal DC/DC is not used at all and external supply voltages are provided for both positive and negative supply voltages. Simple illustrations for each case are shown below.

DAC8775 Both_DCDC_slvsby7.gif Figure 135. DAC8775 With Dual Supplies from Internal DC/DC

Figure 136 illustrates using a single supply from the DAC8775 internal DC/DC and the other supply from an external source. In this example the VNEG_IN_x supply is the input being supplied by an external supply, or ground for unipolar output spans. A similar scheme could be used if VPOS_IN_x was supplied by an external supply and VNEG_IN_x was supplied by the internal DC/DC.

DAC8775 Sing_DCDC_slvsby7.gif Figure 136. DAC8775 With Single Supply from Internal DC/DC

The scheme in Figure 137 should be used if the internal DC/DC is not used at all and external supplies are selected for VPOS_IN_x and VNEG_IN_x. When using external supplies for VPOS_IN_x it is important that VPOS_IN_x, PVDD, and AVDD nodes are tied to the same voltage potential with the same ramp-rate.

DAC8775 No_DCDC_slvsby7.gif Figure 137. DAC8775 with External Supplies