JAJSD57F February   2006  – September 2016 DIX4192

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 RESET Operation
      2. 9.3.2 Master and Reference Clocks
      3. 9.3.3 Audio Serial Port Operation
      4. 9.3.4 Overview of the AES3 Digital Audio Interface Protocol
      5. 9.3.5 Digital Interface Transmitter (DIT) Operation
      6. 9.3.6 Digital Interface Receiver (DIR) Operation
      7. 9.3.7 General-Purpose Digital Outputs
      8. 9.3.8 Interrupt Output
    4. 9.4 Device Functional Modes
      1. 9.4.1 Host Interface Operation: Serial Peripheral Interface (SPI) Mode
      2. 9.4.2 Host Interface Operation: PHILIPS I2C Mode
    5. 9.5 Register Maps
      1. 9.5.1 Register and Data Buffer Organization
      2. 9.5.2 Control Registers
        1. 9.5.2.1 Registers 1F through 28: Q-Channel Sub-Code Data Registers
        2. 9.5.2.2 Registers 29 through 2C: IEC61937 PC/PD Burst Preamble
      3. 9.5.3 Channel Status and User Data Buffer Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Digital Audio Transformer Vendors
      2. 10.1.2 Receiver Input Interfacing
      3. 10.1.3 Transmitter Output Interfacing
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Differential Line Inputs and Output
        2. 10.2.2.2 Serial Ports
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 13.1.2 開発サポート
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Pin Configuration and Functions

PFB Package
48-Pin TQFP
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
AESOUT 34 O DIT buffered AES3-encoded data
AGND 10 GND DIR comparator and PLL power-supply ground
BCKA 37 I/O Audio serial port A bit clock
BCKB 48 I/O Audio serial port B bit clock
BGND 44 GND Substrate ground, connect to AGND (pin 10)
BLS 35 I/O DIT block start clock
CCLK/SCL 20 I Serial data clock for SPI mode or I2C mode
CDIN/A1 21 I SPI port serial data input or programmable slave address for I2C mode
CDOUT/SDA 22 I/O SPI port serial data output (tri-state output) or serial data I/O for I2C mode
CPM 18 I Control port mode, 0 = SPI mode, 1 = I2C mode
CS/A0 19 I Chip select (active low) for SPI mode or programmable slave address for I2C mode
DGND1 16 GND Digital core ground
DGND2 30 GND DIR line receiver bias and DIT line driver digital ground
DGND3 43 GND Logic I/O ground
GPO1 26 O General-purpose output 1
GPO2 27 O General-purpose output 2
GPO3 28 O General-purpose output 3
GPO4 29 O General-purpose output 4
INT 23 O Interrupt flag (open-drain, active low)
LOCK 11 O DIR PLL lock flag (active low)
LRCKA 38 I/O Audio serial Port A left/right clock
LRCKB 47 I/O Audio serial Port B left/right clock
MCLK 25 I Master clock
NC 14, 15, 41 — No internal signal connection, internally bonded to ESD pad
RST 24 I Reset (active low)
RX1+ 1 I Line receiver 1, noninverting input
RX1– 2 I Line receiver 1, inverting input
RX2+ 3 I Line receiver 2, noninverting input
RX2– 4 I Line receiver 2, inverting input
RX3+ 5 I Line receiver 3, noninverting input
RX3– 6 I Line receiver 3, inverting input
RX4+ 7 I Line receiver 4, noninverting input
RX4– 8 I Line receiver 4, inverting input
RXCKI 13 I DIR reference clock
RXCKO 12 O DIR recovered master clock (tri-state output)
SDINA 39 I Audio serial Port A data input
SDINB 46 I Audio serial Port B data input
SDOUTA 40 O Audio serial Port A data output
SDOUTB 45 O Audio serial Port B data output
SYNC 36 O DIT internal sync clock
TX+ 32 O DIT line driver noninverting output
TX– 31 O DIT line driver inverting output
VCC 9 PWR DIR comparator and PLL power supply, 3.3-V nominal
VDD18 17 PWR Digital core supply, 1.8-V nominal
VDD33 33 PWR DIR line receiver bias and DIT line driver supply, 3.3-V nominal
VIO 42 PWR Logic I/O supply, 1.65 V to 3.6 V
(1) I = Input, O = Output, PWR = Power, GND = Ground