JAJSD57F February   2006  – September 2016 DIX4192

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 RESET Operation
      2. 9.3.2 Master and Reference Clocks
      3. 9.3.3 Audio Serial Port Operation
      4. 9.3.4 Overview of the AES3 Digital Audio Interface Protocol
      5. 9.3.5 Digital Interface Transmitter (DIT) Operation
      6. 9.3.6 Digital Interface Receiver (DIR) Operation
      7. 9.3.7 General-Purpose Digital Outputs
      8. 9.3.8 Interrupt Output
    4. 9.4 Device Functional Modes
      1. 9.4.1 Host Interface Operation: Serial Peripheral Interface (SPI) Mode
      2. 9.4.2 Host Interface Operation: PHILIPS I2C Mode
    5. 9.5 Register Maps
      1. 9.5.1 Register and Data Buffer Organization
      2. 9.5.2 Control Registers
        1. 9.5.2.1 Registers 1F through 28: Q-Channel Sub-Code Data Registers
        2. 9.5.2.2 Registers 29 through 2C: IEC61937 PC/PD Burst Preamble
      3. 9.5.3 Channel Status and User Data Buffer Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Digital Audio Transformer Vendors
      2. 10.1.2 Receiver Input Interfacing
      3. 10.1.3 Transmitter Output Interfacing
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Differential Line Inputs and Output
        2. 10.2.2.2 Serial Ports
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 13.1.2 開発サポート
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Power supply VDD18 –0.3 2 V
VDD33 –0.3 4
VIO –0.3 4
VCC –0.3 4
Digital input voltage: digital logic RXCKI, CPM, CS, CCLK, CDIN, CDOUT, INT, RST, MCLK, BLS, SYNC, BCKA, BCKB, LRCKA, LRCKB, SDINA, SDINB –0.3 (VIO + 0.3) V
Line receiver input voltage (per pin) RX1+, RX1–, RX2+, RX2–, RX3+, RX3–, RX4+, RX4– (VDD33 + 0.3) VPP
Input current (all pins except power and ground) ±10 mA
Ambient operating temperature, TA –40 85 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD18 1.8-V power-supply voltage 1.65 1.8 1.95 V
VDD33 3.3-V power-supply voltage 3 3.3 3.6 V
VCC DIR comparator and PLL power-supply voltage 3 3.3 3.6 V
VIO Logic I/O power-supply voltage 1.65 3.3 3.6 V
TA Ambient operating temperature –40 85 °C

8.4 Thermal Information

THERMAL METRIC(1) DIX4192 UNIT
PFB (TQFP)
48 PINS
RθJA Junction-to-ambient thermal resistance 62.0 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 12.8 °C/W
RθJB Junction-to-board thermal resistance 27.9 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 27.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

8.5 Electrical Characteristics

all specifications are at TA = 25°C, VDD18 = 1.8 V, VDD33 = 3.3 V, VIO = 3.3 V, and VCC = 3.3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL I/O CHARACTERISTICS (ALL I/O PINS EXCEPT LINE RECEIVERS AND LINE DRIVER)
VIH High-level input voltage 0.7 × VIO VIO V
VIL Low-level input voltage 0 0.3 × VIO V
IIH High-level input current IO = –4 mA, MUTE, SDINA, and SDINB pins 0.5 25 μA
IO = –4 mA, all other pins 0.5 10
IIL Low-level input current IO = 4 mA 0.5 10 μA
VOH High-level output voltage 0.8 × VIO VIO V
VOL Low-level output voltage 0 0.2 × VIO V
CIN Input capacitance 3 pF
LINE RECEIVER INPUTS (RX1+, RX1–, RX2+, RX2–, RX3+, RX3–, RX4+, RX4–)
VTH Differential input sensitivity Voltage across a given differential input pair 150 200 mV
VHY Input hysteresis 150 mV
LINE DRIVER OUTPUTS (TX+, TX–)
VTXO Differential output voltage RL = 110 Ω across TX+ and TX– 5.4 VPP
MASTER CLOCK INPUT
fMCLK Master clock input (MCLK) frequency 1 27.7 MHz
fMCLKD Master clock input (MCLK) duty cycle 45% 55%
DIGITAL AUDIO INTERFACE RECEIVER (DIR)
PLL lock range TA = 25°C 20 216 kHz
fRXCKI Reference clock input (RXCKI) frequency 3.5 27.7 MHz
fRXCKID Reference clock input (RXCKI) duty cycle 45% 55%
fRXCKO Recovered clock output (RXCKO) frequency 3.5 27.7 MHz
fRXCKOD Recovered clock output (RXCKO) duty cycle 45% 55%
Recovered clock output (RXCKO) intrinsic jitter Measured cycle-to-cycle 250 ps RMS
DIGITAL AUDIO INTERFACE TRANSMITTER (DIT)
Intrinsic output jitter Measured cycle-to-cycle 200 ps RMS
POWER SUPPLIES
Supply current: initial startup All blocks powered down by default
IDD18S VDD18 = 1.8 V 10 μA
IDD33S VDD33 = 3.3 V 10
IIOS VIO = 3.3 V 300
ICCS VCC = 3.3 V 10
Supply current: quiescent All blocks powered up with no clocks applied
IDD18Q VDD18 = 1.8 V 2.3 mA
IDD33Q VDD33 = 3.3 V 0.6
IIOQ VIO = 3.3 V 0.3
ICCQ VCC = 3.3 V 6.3
Supply current: dynamic All blocks powered up, fS = 48 kHz
IDD18D VDD18 = 1.8 V 5.1 mA
IDD33D VDD33 = 3.3 V 14.1
IIOD(1) VIO = 3.3 V 46
ICCD VCC = 3.3 V 7.4
Supply current: high sampling rate All blocks powered up, fS = 192 kHz
IDD18H VDD18 = 1.8 V 6.7 mA
IDD33H VDD33 = 3.3 V 15
IIOH(1) VIO = 3.3 V 47
ICCH VCC = 3.3 V 7.5
Total power dissipation: initial startup All blocks powered down by default 1 mW
Total power dissipation: quiescent All blocks powered up with no clocks applied 28 mW
Total power dissipation: dynamic All blocks powered up, fS = 48 kHz 233 mW
Total power dissipation: high sampling rate All blocks powered up, fS = 192 kHz 242 mW
(1) The typical VIO supply current is measured using the DIX4192EVM evaluation module with loading from the DAIMB motherboard circuitry. VIO supply current is dependent upon the loading on the logic output pins.

8.6 Timing Requirements

MIN NOM MAX UNIT
AUDIO SERIAL PORTS (PORT A AND PORT B)
fLRCK LRCK clock frequency 0 216 kHz
tLRCKD LRCK clock duty cycle 50%
fBCK BCK clock frequency 0 13.824 MHz
tBCKH BCK high pulse duration 10 ns
tBCKL BCK low pulse duration 10 ns
tAIS Audio data Input (SDIN) set-up time 10 ns
tAISH Audio data input (SDIN) hold time 10 ns
tADD Audio data output (SDOUT) delay 10 ns
HOST INTERFACE: SPI MODE
fCCLK Serial clock (CCLK) frequency 0 40 MHz
tCSCR CS falling to CCLK rising 8 ns
tCFCS CCLK falling to CS rising 7 ns
tCDS CDIN data set-up time 7 ns
tCDH CDIN data hold time 6 ns
tCFDO CCLK falling to CDOUT data valid 3 ns
tCSZ CS rising to CDOUT high-impedance 3 ns
HOST INTERFACE: I2C STANDARD MODE(1)
fSCL SCL clock frequency 0 100 kHz
tHDSTA Hold time repeated START condition 4 μs
tLOW Low period of SCL clock 4.7 μs
tHIGH High period of SCL clock 4 μs
tSUSTA Set-up time repeated START condition 4.7 μs
tHDDAT Data hold time 0(2) 3.45(4) μs
tSUDAT Data set-up time 250 ns
tR Rise time for both SDA and SDL 1000 ns
tF Fall time for both SDA and SDL 300 ns
tSUSTO Set-up time for STOP condition 4 μs
tBUF Bus free time between START and STOP 4.7 μs
CB Capacitive load for each bus line 400 pF
VNL Noise margin at low level (including hysteresis) 0.1 × VIO V
VNH Noise margin at high level (including hysteresis) 0.2 × VIO V
HOST INTERFACE: I2C FAST MODE(1)
fSCL SCL clock frequency 0 400 kHz
tHDSTA Hold time repeated START condition 0.6 μs
tLOW Low period of SCL clock 1.3 μs
tHIGH High period of SCL clock 0.6 μs
tSUSTA Set-up time repeated START condition 0.6 μs
tHDDAT Data hold time 0(2) 0.9(4) μs
tSUDAT Data set-up time 100(5) ns
tR Rise time for both SDA and SDL 20 + 0.2CB (3) 300 ns
tF Fall time for both SDA and SDL 20 + 0.2CB (3) 300 ns
tSUSTO Set-up time for STOP condition 0.6 μs
tBUF Bus free time between START and STOP 1.3 μs
tSP Spike pulse duration suppressed by input filter 0 50 ns
CB Capacitive load for each bus Line 400 pF
VNL Noise margin at low level (including hysteresis) 0.1 × VIO V
VNH Noise margin at high level (including hysteresis) 0.2 × VIO V
(1) All values referred to the VIH minimum and VIL maximum levels listed in the Digital I/O Characteristics section of this table.
(2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH minimum input level) to bridge the undefined region of the falling edge of SCL.
(3) CB is defined as the total capacitance of one bus line in picofarads (pF). If mixed with High-Speed mode devices, faster fall times are allowed.
(4) The maximum tHDDAT has only to be met if the device does not stretch the Low period (tLOW) of the SCL signal.
(5) A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement that tSUDAT be 250 ns (minimum) must then be met. For the DIX4192, this condition is automatically the case, because the device does not stretch the Low period of the SCL signal.
DIX4192 ec_time_audio_bfs031.gif Figure 1. Audio Serial Port Timing
DIX4192 ec_time_spi_bfs031.gif Figure 2. SPI Timing
DIX4192 ec_time_i2c_bfs031.gif Figure 3. I2C Standard and Fast Mode Timing

8.7 Typical Characteristics

DIX4192 prd_dir_jit_atn_bfs031.gif
Figure 4. DIR Jitter Attenuation Characteristics
DIX4192 prd_dir_jit_tol_bfs031.gif
Figure 5. DIR Jitter Tolerance Plot