JAJSEU8B February   2018  – April 2018 DLPC3432

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     概略回路図
      1.      Device Images
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions – Board Level Test, Debug, and Initialization
    2.     Pin Functions – Parallel Port Input Data and Control
    3.     Pin Functions - DSI Input Data and Clock
    4.     Pin Functions – DMD Reset and Bias Control
    5.     Pin Functions – DMD Sub-LVDS Interface
    6.     Pin Functions – Peripheral Interface
    7.     Pin Functions – GPIO Peripheral Interface
    8.     Pin Functions – Clock and PLL Support
    9.     Pin Functions – Power and Ground
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics Over Recommended Operating Conditions
    6. 6.6  Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Characteristics
    8. 6.8  High-Speed Sub-LVDS Electrical Characteristics
    9. 6.9  Low-Speed SDR Electrical Characteristics
    10. 6.10 System Oscillators Timing Requirements
    11. 6.11 Power-Up and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 BT656 Interface General Timing Requirements
    15. 6.15 DSI Host Timing Requirements
    16. 6.16 Flash Interface Timing Requirements
  7. Parameter Measurement Information
    1. 7.1 HOST_IRQ Usage Model
    2. 7.2 Input Source
      1. 7.2.1 Input Source - Frame Rates and 3D Display Orientation
      2. 7.2.2 Parallel Interface Supports Six Data Transfer Formats
        1. 7.2.2.1 PDATA Bus – Parallel Interface Bit Mapping Modes
        2. 7.2.2.2 DSI Interface - Supported Data Transfer Formats
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Interface Timing Requirements
        1. 8.3.1.1 Parallel Interface
        2. 8.3.1.2 Display Serial Interface DSI
    4. 8.4 Serial Flash Interface
      1. 8.4.1  Serial Flash Programming
      2. 8.4.2  SPI Signal Routing
      3. 8.4.3  I2C Interface Performance
      4. 8.4.4  Content-Adaptive Illumination Control
      5. 8.4.5  Local Area Brightness Boost
      6. 8.4.6  3D Glasses Operation
      7. 8.4.7  DMD (Sub-LVDS) Interface
      8. 8.4.8  DLPC3432 System Design Consideration – Application Notes
      9. 8.4.9  Calibration and Debug Support
      10. 8.4.10 DMD Interface Considerations
    5. 8.5 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 System Power-Up and Power-Down Sequence
    2. 10.2 DLPC3432 Power-Up Initialization Sequence
    3. 10.3 DMD Fast PARK Control (PARKZ)
    4. 10.4 Hot Plug Usage
    5. 10.5 Maximum Signal Transition Time
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1  PCB Layout Guidelines for Internal ASIC PLL Power
      2. 11.1.2  DLPC3432 Reference Clock
        1. 11.1.2.1 Recommended Crystal Oscillator Configuration
        2. 11.1.2.2 PCB Layout Guidelines for DSI Interface
      3. 11.1.3  General PCB Recommendations
      4. 11.1.4  General Handling Guidelines for Unused CMOS-Type Pins
      5. 11.1.5  Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      6. 11.1.6  Number of Layer Changes
      7. 11.1.7  Stubs
      8. 11.1.8  Terminations
      9. 11.1.9  Routing Vias
      10. 11.1.10 Thermal Considerations
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 デバイスの項目表記
        1. 12.1.2.1 デバイスのマーキング
      3. 12.1.3 ビデオ・タイミング・パラメータの定義
    2. 12.2 関連リンク
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
発注情報

Flash Interface Timing Requirements

The DLPC3432 ASIC flash memory interface consists of a SPI flash serial interface with a programmable clock rate. The DLPC3432 can support 1- to 16-Mb flash memories.(1)(2)
MIN MAX UNIT
fclock Clock frequency, SPI_CLK See (3) 1.42 36.0 MHz
tp_clkper Clock period, SPI_CLK 50% reference points 704 27.7 ns
tp_wh Pulse duration low, SPI_CLK 50% reference points 352 ns
tp_wl Pulse duration high, SPI_CLK 50% reference points 352 ns
tt Transition time – all signals 20% to 80% reference points 0.2 3.0 ns
tp_su Setup time – SPI_DIN valid before SPI_CLK falling edge 50% reference points 10.0 ns
tp_h Hold time – SPI_DIN valid after SPI_CLK falling edge 50% reference points 0.0 ns
tp_clqv SPI_CLK clock falling edge to output valid time – SPI_DOUT and SPI_CSZ 50% reference points 1.0 ns
tp_clqx SPI_CLK clock falling edge output hold time – SPI_DOUT and SPI_CSZ 50% reference points –3.0 3.0 ns
Standard SPI protocol is to transmit data on the falling edge of SPI_CLK and capture data on the rising edge. The DLPC3432 does transmit data on the falling edge, but it also captures data on the falling edge rather than the rising edge. This provides support for SPI devices with long clock-to-Q timing. DLPC3432 hold capture timing has been set to facilitate reliable operation with standard external SPI protocol devices.
With the above output timing, DLPC3432 provides the external SPI device 8.2-ns input set-up and 8.2-ns input hold, relative to the rising edge of SPI_CLK.
This range include the 200 ppm of the external oscillator (but no jitter).
DLPC3432 tim_flash_mem_LPS038.gifFigure 7. Flash Interface Timing