JAJSF42A April   2018  – July 2018 DLPC3478

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      標準的なスタンドアロン・システム
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions – Board Level Test, Debug, and Initialization
    2.     Pin Functions – Parallel Port Input Data and Control
    3.     Pin Functions - DSI Input Data and Clock
    4.     Pin Functions – DMD Reset and Bias Control
    5.     Pin Functions – DMD Sub-LVDS Interface
    6.     Pin Functions – Peripheral Interface
    7.     Pin Functions – GPIO Peripheral Interface
    8.     Pin Functions – Clock and PLL Support
    9.     Pin Functions – Power and Ground
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics over Recommended Operating Conditions
    6. 6.6  Electrical Characteristics
    7. 6.7  High-Speed Sub-LVDS Electrical Characteristics
    8. 6.8  Low-Speed SDR Electrical Characteristics
    9. 6.9  System Oscillators Timing Requirements
    10. 6.10 Power-Up and Reset Timing Requirements
    11. 6.11 Parallel Interface Frame Timing Requirements
    12. 6.12 Parallel Interface General Timing Requirements
    13. 6.13 BT656 Interface General Timing Requirements
    14. 6.14 Flash Interface Timing Requirements
  7. Parameter Measurement Information
    1. 7.1 HOST_IRQ Usage Model
    2. 7.2 Input Source
      1. 7.2.1 Input Source - Frame Rates and 3-D Display Orientation
      2. 7.2.2 Parallel Interface Supports Six Data Transfer Formats
        1. 7.2.2.1 PDATA Bus – Parallel Interface Bit Mapping Modes
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pattern Display
        1. 8.3.1.1 External Pattern Mode
          1. 8.3.1.1.1 8-bit Monochrome Patterns
          2. 8.3.1.1.2 1-Bit Monochrome Patterns
        2. 8.3.1.2 Internal Pattern Mode
          1. 8.3.1.2.1 Free Running Mode
          2. 8.3.1.2.2 Trigger In Mode
      2. 8.3.2 Interface Timing Requirements
        1. 8.3.2.1 Parallel Interface
    4. 8.4 Serial Flash Interface
      1. 8.4.1  Serial Flash Programming
      2. 8.4.2  SPI Signal Routing
      3. 8.4.3  I2C Interface Performance
      4. 8.4.4  Content-Adaptive Illumination Control
      5. 8.4.5  Local Area Brightness Boost
      6. 8.4.6  3-D Glasses Operation
      7. 8.4.7  DMD (Sub-LVDS) Interface
      8. 8.4.8  Calibration and Debug Support
      9. 8.4.9  DMD Interface Considerations
      10. 8.4.10 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 DLPC3478 System Design Consideration
    2. 9.2 Typical Application
      1. 9.2.1 3D Depth Scanner with DLP Using External Pattern Streaming Mode
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 3D Depth Scanner Using Internal Pattern Streaming Mode
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 System Power-Up and Power-Down Sequence
    2. 10.2 DLPC3478 Power-Up Initialization Sequence
    3. 10.3 DMD Fast PARK Control (PARKZ)
    4. 10.4 Hot Plug Usage
    5. 10.5 Maximum Signal Transition Time
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout Guidelines for Internal ASIC PLL Power
      2. 11.1.2 DLPC3478 Reference Clock
        1. 11.1.2.1 Recommended Crystal Oscillator Configuration
      3. 11.1.3 General PCB Recommendations
      4. 11.1.4 General Handling Guidelines for Unused CMOS-Type Pins
      5. 11.1.5 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      6. 11.1.6 Number of Layer Changes
      7. 11.1.7 Stubs
      8. 11.1.8 Terminations
      9. 11.1.9 Routing Vias
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 デバイスの項目表記
        1. 12.1.2.1 デバイスのマーキング
      3. 12.1.3 ビデオ・タイミング・パラメータの定義
    2. 12.2 関連リンク
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
発注情報

Pin Configuration and Functions

ZEZ Package
201-Pin NFBGA
Bottom View
DLPC3478 po_201_LPS038.gif
DLPC3478 table_DLPC3435_LPS038.gif

Pin Functions – Board Level Test, Debug, and Initialization

PIN I/O DESCRIPTION
NAME NUMBER
HWTEST_EN C10 I6 Manufacturing test enable signal. Connect this signal directly to ground on the PCB for normal operation.
PARKZ C13 I6 DMD fast PARK control (active low Input) (hysteresis buffer). PARKZ must be set high to enable normal operation. Set PARKZ high prior to releasing RESETZ (that is, prior to the low-to-high transition on the RESETZ input). Set PARKZ low for a minimum of 32 µs before any power is removed from the DLPC3478 such that the fast DMD PARK operation can be completed. Note for PARKZ, use fast PARK control only when loss of power is eminent and beyond the control of the host processor (for example, when the external power source has been disconnected or the battery has dropped below a minimum level). The longest lifetime of the DMD may not be achieved with the fast PARK operation. The longest lifetime is achieved with a normal PARK operation. Because of this, PARKZ is typically used in conjunction with a normal PARK request control input through GPIO_08. The difference being that when the host sets PROJ_ON low, which connects to both GPIO_08 and the DLPA200x or DLPA300x PMIC chip, the takes much longer than 32 µs to park the mirrors. The DLPA200x or DLPA300x holds on all power supplies, and keep RESETZ high, until the longer mirror parking has completed. This longer mirror parking time, of up to 500 µs, ensures the longest DMD lifetime and reliability.
The DLPA200x or DLPA300x monitors power to the and detects an eminent power loss condition and drives the PARKZ signal accordingly.
Reserved P12 I6 TI internal use. Leave unconnected.
Reserved P13 I6 TI internal use. Leave unconnected.
Reserved N13(1) O1 TI internal use. Leave unconnected.
Reserved N12(1) O1 TI internal use. Leave unconnected.
Reserved M13 I6 TI internal use. Leave unconnected.
Reserved N11 I6 TI internal use. Leave unconnected.
Reserved P11 I6 TI internal use
This pin must be tied to ground, through an external 8-kΩ, or less, resistor for normal operation. Failure to tie this pin low during normal operation causes startup and initialization problems.
RESETZ C11 I6 power-on reset (active low input) (hysteresis buffer). Self-configuration starts when a low-to-high transition is detected on RESETZ. All ASIC power and clocks must be stable before this reset is de-asserted. Note that the following signals become tri-stated while RESETZ is asserted:
SPI0_CLK, SPI0_DOUT, SPI0_CSZ0,
SPI0_CSZ1, and GPIO(19:00)
External pullups or downs (as appropriate) are typically added to all tri-stated output signals listed (including bidirectional signals to be configured as outputs) to avoid floating ASIC outputs during reset if connected to devices on the PCB that can malfunction. For SPI, at a minimum, any chip selects connected to the devices typically have a pullup.
Unused bidirectional signals can be functionally configured as outputs to avoid floating ASIC inputs after RESETZ is set high.
The following signals are forced to a logic low state while RESETZ is asserted and corresponding I/O power is applied:
LED_SEL_0, LED_SEL_1 and DMD_DEN_ARSTZ
No signals operate in active state while RESETZ is asserted.
Note that no I2C activity is permitted for a minimum of 500 ms after RESETZ (and PARKZ) are set high.
TSTPT_0 R12 B1 Test pin 0 (includes weak internal pulldown) – tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ, and then driven as an output.
Normal use: reserved for test output. Leave open for normal use.
Note: Do not apply an external pullup component to this pin to avoid putting the in a test mode.
Without external pullup (2)
Feeds TMSEL(0)
With external pullup(3)
Feeds TMSEL(0)
TSTPT_1 R13 B1 Test pin 1 (includes weak internal pulldown) – tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.
Normal use: reserved for test output. Leave open for normal use.
Note: Do not apply an external pullup component to this pin to avoid putting the in a test mode.
Without external pullup(2)
Feeds TMSEL(1)
With external pullup(3)
Feeds TMSEL(1)
TSTPT_2 R14 B1 Test pin 2 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.
Normal use: reserved for test output. Leave open for normal use.
Note: Do not apply an external pullup component to this pin to avoid putting the in a test mode.
Without external pullup(2)
Feeds TMSEL(2)
With external pullup(3)
Feeds TMSEL(2)
TSTPT_3 R15 B1 Test pin 3 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.
Normal use: reserved for for test output. Leave open for normal use.
TSTPT_4 P14 B1 Test pin 4 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.
Normal use: reserved for test output. Leave open for normal use.
Reserved for TRIG_OUT_1 signal (Output).
TSTPT_5 P15 B1 Test pin 5 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.
Normal use: reserved for test output. Leave open or unconnected for normal use.
TSTPT_6 N14 B1 Test pin 6 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.
Normal use: reserved for test output. Leave open for normal use.
Alternative use: none. External logic shall not unintentionally pull this pin high to avoid putting the in a test mode.
TSTPT_7 N15 B1 Test pin 7 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.
Normal use: reserved for test output. Leave open for normal use.
If operation does not call for an external pullup and there is no external logic that might overcome the weak internal pulldown resistor, then this I/O can be left open or unconnected for normal operation. If operation does not call for an external pullup, but there is external logic that might overcome the weak internal pulldown resistor, then an external pulldown resistor is recommended to ensure a logic low.
External pullup resistor must be 8 kΩ, or less, for pins with internal pullup or down resistors.
If operation does not call for an external pullup and there is no external logic that might overcome the weak internal pulldown resistor, then the TSTPT I/O can be left open/ unconnected for normal operation. If operation does not call for an external pullup, but there is external logic that might overcome the weak internal pulldown resistor, then an external pulldown resistor is recommended to ensure a logic low.

Pin Functions – Parallel Port Input Data and Control(1)(4)

PIN I/O DESCRIPTION
NAME NUMBER PARALLEL RGB MODE BT656 INTERFACE MODE
PCLK P3 I11 Pixel clock(6) Pixel clock(6)
PDM_CVS_TE N4 B5 Parallel data mask(3) Unused(2)
VSYNC_WE P1 I11 Vsync(5) Unused(2)
HSYNC_CS N5 I11 Hsync(5) Unused(2)
DATAEN_CMD P2 I11 Data Valid(5) Unused(2)
(TYPICAL RGB 888)
PDATA_0
PDATA_1
PDATA_2
PDATA_3
PDATA_4
PDATA_5
PDATA_6
PDATA_7
K2
K1
L2
L1
M2
M1
N2
N1
I11 Blue (bit weight 1)
Blue (bit weight 2)
Blue (bit weight 4)
Blue (bit weight 8)
Blue (bit weight 16)
Blue (bit weight 32)
Blue (bit weight 64)
Blue (bit weight 128)
BT656_Data (0)
BT656_Data (1)
BT656_Data (2)
BT656_Data (3)
BT656_Data (4)
BT656_Data (5)
BT656_Data (6)
BT656_Data (7)
(TYPICAL RGB 888)
PDATA_8
PDATA_9
PDATA_10
PDATA_11
PDATA_12
PDATA_13
PDATA_14
PDATA_15
R1
R2
R3
P4
R4
P5
R5
P6
I11 Green (bit weight 1)
Green (bit weight 2)
Green (bit weight 4)
Green (bit weight 8)
Green (bit weight 16)
Green (bit weight 32)
Green (bit weight 64)
Green (bit weight 128)
Unused
(TYPICAL RGB 888)
PDATA_16
PDATA_17
PDATA_18
PDATA_19
PDATA_20
PDATA_21
PDATA_22
PDATA_23
R6
P7
R7
P8
R8
P9
R9
P10
I11 Red (bit weight 1)
Red (bit weight 2)
Red (bit weight 4)
Red (bit weight 8)
Red (bit weight 16)
Red (bit weight 32)
Red (bit weight 64)
Red (bit weight 128)
Unused
3DR N6 3D reference
  • For 3D applications: left or right 3D reference (left = 1, right = 0). To be provided by the host when a 3D command is not provided. Must transition in the middle of each frame (no closer than 1 ms to the active edge of VSYNC)
  • For light control applications: Reserved for TRIG_IN (Input). Applicable in Internal Pattern Streaming Mode only.
  • If a 3D or light control application are not being used (i.e. 3DR input is not being used), then this input is typically pulled low through an external resister (8 kΩ or less).
PDATA(23:0) bus mapping is pixel format and source mode dependent. See later sections for details.
Ground unused inputs or pull down to ground through an external resistor (8 kΩ or less).
The parallel data mask signal input is optional for parallel interface operations. Ground unused inputs or pull down to ground through an external resistor (8 kΩ or less).
PDM_CVS_TE is optional for parallel interface operation. Ground unused inputs or pull down to ground through an external resistor (8 kΩ or less).
VSYNC, HSYNC, and DATAEN polarity is software programmable.
Pixel clock capture edge is software programmable.

Pin Functions - DSI Input Data and Clock(1)

Added PIN I/O DESCRIPTION
NAME NUMBER MIPI DSI MODE
DCLKN
DCLKP
E2
E1
B10 Not supported in this device. This pin must remain unconnected and left floating.
DD0N
DD0P
DD1N
DD1P
DD2N
DD2P
DD3N
DD3P
G2
G1
F2
F1
D2
D1
C2
C1
B10 Not supported in this device. This pin must remain unconnected and left floating.
RREF F3 Not supported in this device. This pin must remain unconnected and left floating.
This device supports none of these pins. These pins must remain unconnected and left floating.

Pin Functions – DMD Reset and Bias Control

PIN I/O DESCRIPTION
NAME NUMBER
DMD_DEN_ARSTZ B1 O2 DMD driver enable (active high)/ DMD reset (active low). Assuming the corresponding I/O power is supplied, this signal is driven low after the DMD is parked and before power is removed from the DMD. If the 1.8-V power to the is independent of the 1.8-V power to the DMD, then TI recommends a weak, external pulldown resistor to hold the signal low in the event power is inactive while DMD power is applied.
DMD_LS_CLK A1 O3 DMD, low speed interface clock
DMD_LS_WDATA A2 O3 DMD, low speed serial write data
DMD_LS_RDATA B2 I6 DMD, low speed serial read data

Pin Functions – DMD Sub-LVDS Interface

PIN I/O DESCRIPTION
NAME NUMBER
DMD_HS_CLK_P
DMD_HS_CLK_N
A7
B7
O4 DMD high speed interface
DMD_HS_WDATA_H_P
DMD_HS_WDATA_H_N
DMD_HS_WDATA_G_P
DMD_HS_WDATA_G_N
DMD_HS_WDATA_F_P
DMD_HS_WDATA_F_N
DMD_HS_WDATA_E_P
DMD_HS_WDATA_E_N
DMD_HS_WDATA_D_P
DMD_HS_WDATA_D_N
DMD_HS_WDATA_C_P
DMD_HS_WDATA_C_N
DMD_HS_WDATA_B_P
DMD_HS_WDATA_B_N
DMD_HS_WDATA_A_P
DMD_HS_WDATA_A_N
A3
B3
A4
B4
A5
B5
A6
B6
A8
B8
A9
B9
A10
B10
A11
B11
O4 DMD high speed interface lanes, write data bits: (The true numbering and application of the DMD_HS_DATA pins are software configuration dependent)

Pin Functions – Peripheral Interface(1)

PIN I/O DESCRIPTION
NAME NUMBER
CMP_OUT A12 I6 Successive approximation ADC comparator output ( Input). Assumes a successive approximation ADC is implemented with a WPC light sensor and/or a thermistor feeding one input of an external comparator and the other side of the comparator is driven from the ASIC’s CMP_PWM pin. Typically pulled-down to ground if this function is not used. (hysteresis buffer)
CMP_PWM A15 O1 Successive approximation comparator pulse-duration modulation (output). Supplies a PWM signal to drive the successive approximation ADC comparator used in WPC light-to-voltage sensor applications. Leave unconnected if this function is not used.
HOST_IRQ(2) N8 O9 Host interrupt (output)
HOST_IRQ indicates when the auto-initialization is in progress and most importantly when it completes.
The tri-states this output during reset and assumes that an external pullup is in place to drive this signal to its inactive state.
IIC0_SCL N10 B7 I2C slave (port 0) SCL (bidirectional, open-drain signal with input hysteresis): An external pullup is required. The slave I2C I/Os are 3.6-V tolerant (high-volt-input tolerant) and are powered by VCC_INTF (which can be 1.8, 2.5, or 3.3 V). External I2C pullups must be connected to an equal or higher supply voltage, up to a maximum of 3.6 V (a lower pullup supply voltage would not likely satisfy the VIH specification of the slave I2C input buffers).
Reserved R11 B8 TI internal use. TI recommends an external pullup resistor.
IIC0_SDA N9 B7 I2C slave (port 0) SDA. (bidirectional, open-drain signal with input hysteresis): An external pullup is required. The slave I2C port is the control port of ASIC. The slave I2C I/Os are 3.6-V tolerant (high-volt-input tolerant) and are powered by VCC_INTF (which can be 1.8, 2.5, or 3.3 V). External I2C pullups must be connected to an equal or higher supply voltage, up to a maximum of 3.6 V (a lower pullup supply voltage would not likely satisfy the VIH specification of the slave I2C input buffers).
Reserved R10 B8 TI internal use. TI recommends an external pullup resistor.
LED_SEL_0 B15 O1 LED enable select. Controlled by programmable DMD sequence
Timing
LED_SEL(1:0)
00
01
10
11
Enabled LED
DLPA200x / DLPA300x application
None
Red
Green
Blue
LED_SEL_1 B14 O1 These signals are driven low when RESETZ is asserted and the corresponding I/O power is supplied and continues throughout the auto-initialization process. A weak, external pulldown resistor is still recommended to ensure that the LEDs are disabled when I/O power is not applied.
SPI0_CLK A13 O13 Synchronous serial port 0, clock
SPI0_CSZ0 A14 O13 SPI port 1, chip select 0 (active low output)
TI recommends an external pullup resistor to avoid floating inputs to the external SPI device during ASIC reset assertion.
SPI0_CSZ1 C12 O13 SPI port 1, chip select 1 (active low output)
TI recommends an external pullup resistor to avoid floating inputs to the external SPI device during ASIC reset assertion.
SPI0_DIN B12 I12 Synchronous serial port 0, receive data in
SPI0_DOUT B13 O13 Synchronous serial port 0, transmit data out
External pullup resistor must be 8 kΩ or less.
For more information about usage, see HOST_IRQ Usage Model.

Pin Functions – GPIO Peripheral Interface(1)

PIN I/O DESCRIPTION(2)
NAME NUMBER
GPIO_19 M15 B1 General purpose I/O 19 (hysteresis buffer). Options:
  1. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
  2. MTR_SENSE, Motor Sense (Input): For Focus Motor control applications, this GPIO must be configured as an input to the fed from the focus motor position sensor.
  3. KEYPAD_4 (input): keypad applications
GPIO_18 M14 B1 General purpose I/O 18 (hysteresis buffer). Options:
  1. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise this pin requires an external pullup or pulldown component to avoid a floating GPIO input)
  2. KEYPAD_3 (input): keypad applications
GPIO_17 L15 B1 General purpose I/O 17 (hysteresis buffer). Options:
  1. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
  2. KEYPAD_2 (input): keypad applications
GPIO_16 L14 B1 General purpose I/O 16 (hysteresis buffer). Options:
  1. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
  2. KEYPAD_1 (input): keypad applications
GPIO_15 K15 B1 General purpose I/O 15 (hysteresis buffer). Options:
  1. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
  2. KEYPAD_0 (input): keypad applications
GPIO_14 K14 B1 General purpose I/O 14 (hysteresis buffer). Options:
  1. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
GPIO_13 J15 B1 General purpose I/O 13 (hysteresis buffer). Options:
  1. CAL_PWR (output): Intended to feed the calibration control of the successive approximation ADC light sensor.
  2. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
GPIO_12 J14 B1 General purpose I/O 12 (hysteresis buffer). Options:
  1. (Output) power enable control for LABB light sensor.
  2. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
GPIO_11 H15 B1 General purpose I/O 11 (hysteresis buffer). Options:
  1. (Output): thermistor power enable.
  2. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
GPIO_10 H14 B1 General Purpose I/O 10 (hysteresis buffer). Options:
  1. RC_CHARGE (output): Intended to feed the RC charge circuit of the successive approximation ADC used to control the light sensor comparator.
  2. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
GPIO_09 G15 B1 General purpose I/O 09 (hysteresis buffer). Options:
  1. LS_PWR (active high output): Intended to feed the power control signal of the successive approximation ADC light sensor.
  2. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
GPIO_08 G14 B1 General purpose I/O 08 (hysteresis buffer). Options:
  1. (All) Normal mirror parking request (active low): To be driven by the PROJ_ON output of the host. A logic low on this signal causes the to ASIC to PARK the DMD, but it does not power down the DMD (the DLPA200x or DLPA300x performs that function). The minimum high time is 200 ms. The minimum low time is also 200 ms.
GPIO_07 F15 B1 General purpose I/O 07 (hysteresis buffer). Options:
  1. (Output): LABB output sample and hold sensor control signal.
  2. Light Control: Reserved for TRIG_OUT_2 signal (Output).
  3. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
GPIO_06 F14 B1 General purpose I/O 06 (hysteresis buffer). Option:
  1. Light Control: Reserved for pattern ready signal (Output). Applicable in Internal Pattern Streaming Mode only.
  2. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
GPIO_05 E15 B1 General purpose I/O 05 (hysteresis buffer). Options:
  1. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
GPIO_04 E14 B1 General purpose I/O 04 (hysteresis buffer). Options:
  1. 3D glasses control (output): intended to be used to control the shutters on 3D glasses (Left = 1, Right = 0).
  2. SPI1_CSZ1 (active-low output): optional SPI1 chip select 1 signal. An external pullup resistor is required to deactivate this signal during reset and auto-initialization processes.
  3. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
GPIO_03 D15 B1 General purpose I/O 03 (hysteresis buffer). Options:
  1. SPI1_CSZ0 (active low output): Optional SPI1 chip select 0 signal. An external pullup resistor is required to deactivate this signal during reset and auto-initialization processes.
  2. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
GPIO_02 D14 B1 General purpose I/O 02 (hysteresis buffer). Options:
  1. SPI1_DOUT (output): Optional SPI1 data output signal.
  2. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
GPIO_01 C15 B1 General purpose I/O 01 (hysteresis buffer). Options:
  1. SPI1_CLK (output): Optional SPI1 clock signal.
  2. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
GPIO_00 C14 B1 General purpose I/O 00 (hysteresis buffer). Options:
  1. SPI1_DIN (input): Optional SPI1 data input signal.
  2. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
GPIO signals must be configured through software for input, output, bidirectional, or open-drain. Some GPIO have one or more alternative use modes, which are also software configurable. The reset default for all GPIO is as an input signal. An external pullup is required for each signal configured as open-drain.
general purpose I/O. These GPIO are software configurable.

Pin Functions – Clock and PLL Support

PIN I/O DESCRIPTION
NAME NUMBER
PLL_REFCLK_I H1 I11 Reference clock crystal input. If the application uses an external oscillator instead of a crystal, use this pin as the oscillator input.
PLL_REFCLK_O J1 O5 Reference clock crystal return. If the application uses an external oscillator instead of a crystal, leave this pin unconnected (floating with no added capacitive load).

Pin Functions – Power and Ground(1)

PIN I/O DESCRIPTION
NAME NUMBER
VDD C5, D5, D7, D12, J4, J12, K3, L4, L12, M6, M9, D9, D13, F13, H13, L13, M10, D3, E3 PWR Core power 1.1 V (main 1.1 V)
VDDLP12 C3 PWR Reserved
VSS Common to all package types
C4, D6, D8, D10, E4, E13, F4, G4, G12, H4, H12, J3, J13, K4, K12, L3, M4, M5, M8, M12, G13, C6, C8
Only available on
F6, F7, F8, F9, F10, G6, G7, G8, G9, G10, H6, H7, H8, H9, H10, J6, J7, J8, J9, J10, K6, K7, K8, K9, K10
GND Core ground (eDRAM, I/O ground, thermal ground)
VCC18 C7, C9, D4, E12, F12, K13, M11 PWR All 1.8-V I/O power:
(1.8-V power supply for all I/O other than the host or parallel interface and the SPI flash interface. This includes RESETZ, PARKZ LED_SEL, CMP, GPIO, IIC1, TSTPT, and JTAG pins)
VCC_INTF M3, M7, N3, N7 PWR Host or parallel interface I/O power: 1.8 to 3.3 V (Includes IIC0, PDATA, video syncs, and HOST_IRQ pins)
VCC_FLSH D11 PWR Flash interface I/O power:1.8 to 3.3 V
(Dedicated SPI0 power pin)
VDD_PLLM H2 PWR MCG PLL 1.1-V power
VSS_PLLM G3 RTN MCG PLL return
VDD_PLLD J2 PWR DCG PLL 1.1-V power
VSS_PLLD H3 RTN DCG PLL return
The only power sequencing restrictions are:
  • The VDD supply typically ramps up with a 1-ms minimum rise time.
  • The reverse is needed at power down.

Table 1. I/O Type Subscript Definition

I/O SUPPLY REFERENCE ESD STRUCTURE
SUBSCRIPT DESCRIPTION
1 1.8 LVCMOS I/O buffer with 8-mA drive Vcc18 ESD diode to GND and supply rail
2 1.8 LVCMOS I/O buffer with 4-mA drive Vcc18 ESD diode to GND and supply rail
3 1.8 LVCMOS I/O buffer with 24-mA drive Vcc18 ESD diode to GND and supply rail
4 1.8 sub-LVDS output with 4-mA drive Vcc18 ESD diode to GND and supply rail
5 1.8, 2.5, 3.3 LVCMOS with 4-mA drive Vcc_INTF ESD diode to GND and supply rail
6 1.8 LVCMOS input Vcc18 ESD diode to GND and supply rail
7 1.8-, 2.5-, 3.3-V I2C with 3-mA drive Vcc_INTF ESD diode to GND and supply rail
8 1.8-V I2C with 3-mA drive Vcc18 ESD diode to GND and supply rail
9 1.8-, 2.5-, 3.3-V LVCMOS with 8-mA drive Vcc_INTF ESD diode to GND and supply rail
11 1.8, 2.5, 3.3 LVCMOS input Vcc_INTF ESD diode to GND and supply rail
12 1.8-, 2.5-, 3.3-V LVCMOS input Vcc_FLSH ESD diode to GND and supply rail
13 1.8-, 2.5-, 3.3-V LVCMOS with 8-mA drive Vcc_FLSH ESD diode to GND and supply rail