JAJSGP5A データシート

JAJSGP5A December 2018 – August 2019 DP83825I

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RMQ|24
- MPQF398A

サーマルパッド・メカニカル・データ

発注情報

6 Pin Configuration and Functions

DP83825 RMQ Package

24-Pin QFN

Top View

DP83825I DP83825I_qfn_pin_diagram_v2.gif

DP83825I Pin Functions

PIN		TYPE⁽¹⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾	DESCRIPTION
TX_EN	1	Reset: I, PD Active: I, PD	RMII Transmit Enable: TX_EN is active high signal and is presented on the rising edge of the TX_CLK. TX_EN indicates the presence of valid data inputs on TX_D [1:0].
50MHzOut/LED2	2	Reset: I, PD, S Active: O	RMII Master Mode: 50 MHz Clock Out(default). RMII Slave Mode: LED_2(default). This pin can be configured as GPIO using register configuration.
INTR/PWRDN	3	Reset: I, PU Active: I, PU	Interrupt / Power Down(default): The default function of this pin is power down. Register access is required to configure this pin as an interrupt. In power-down function, an active low signal on this pin places the device in power down mode. When this pin is configured as an interrupt pin, this pin is asserted low when an interrupt condition occurs. The pin has an open-drain output with a weak internal pullup (9.5KΩ). Some applications may require an external pullup resistor.
LED0	4	Reset: I, PD, S Active: O	LED0 : Activity Indication LED indicates transmit and receive activity in addition to the status of the Link. The LED is ON when Link is good. The LED blinks when the transmitter or receiver is active. This pin can also act as GPIO through register configuration. This pin is at 3.3 V always and not linked to voltage supplied to VDDIO pin. This is to avoid external components when operating PHY at VDDIO 1.8 V.
RST_N	5	Reset: I, PU Active: I, PU	RST_N: This pin is an active low reset input. Asserting this pin low for at least 1 μs will force a reset process to occur. Initiation of reset causes strap pins to be re-scanned and resets all the internal registers of the PHY to default value.
VDDA3V3	6	Power	Input Analog Supply: 3.3 V. For decoupling capacitor requirements, refer to the Application and Implementation section.Figure 20
RD_M	7	A	Differential Receive Input (PMD): These differential inputs are automatically configured to accept either 10BASE-Te, 100BASE-TX specific signaling mode
RD_P	8	A
GND	9	GND	Ground: Connect to Ground
TD_M	10	A	Differential Transmit Output (PMD): These differential outputs are configured to either 10BASE-Te, 100BASE-TX signaling mode based on configuration chosen for PHY.
TD_P	11	A
XO	12	A	Crystal Output: Reference Clock output. XO pin is used for crystal only. This pin should be left floating when a CMOS-level oscillator is connected to XI.
XI/50MHzIn	13	A	Crystal / Oscillator Input Clock RMII Master mode: 25-MHz ±50 ppm-tolerance crystal or oscillator clock RMII Slave mode: 50-MHz ±50 ppm-tolerance CMOS-level oscillator clock
RBIAS	14	A	RBIAS value 6.49 KΩ 1% connected to ground
MDIO	15	Reset: I, PU-10K Active: IO, PU-10K	Management Data I/O: Bidirectional management data signal that may be source by the management station or the PHY. This pin has internal pullup of 10 KΩ. External pullup of up to 2.2 KΩ can be added if needed
MDC	16	Reset: I, PD Active: I, PD	Management Data Clock: Synchronous clock to the MDIO serial management input/output data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25 MHz. There is no minimum clock rate.
RX_D1	17	Reset: I, PD, S Active: O	RMII Receive Data: Symbols received on the cable are decoded and presented on these pins synchronous to reference clock. They contain valid data when RX_DV is asserted.
RX_D0	18	Reset: I, PD, S Active: O	RMII Receive Data: Symbols received on the cable are decoded and presented on these pins synchronous to reference clock. They contain valid data when RX_DV is asserted.
VDDIO	19	Power	I/O Supply : 3.3 V/1.8 V. For decoupling capacitor requirements, refer to the Application and Implementation section.
CRS_DV	20	Reset: I, PD, S Active: O	Carrier Sense / Receive Data Valid: This pin combines the RMII Carrier and Receive Data Valid indications.
GND	21	GND	Ground pin
RX_ER	22	Reset: I, PD, S Active: O	RMII Receive Error: This pin indicates an error symbol has been detected within a received packet in RMII mode. RX_ER is asserted high synchronously to the rising edge of the reference clock. This pin is not required to be used by the MAC in RMII because the PHY will automatically corrupting data on a receive error.
TX_D0	23	Reset: I, PD Active: I, PD	RMII Transmit Data: TX_D[1:0] received from the MAC and shall be synchronous to the rising edge of the reference clock.
TX_D1	24	Reset: I, PD Active: I, PD

(1) The pin functions are defined below:
Type I: Input
Type O: Output
Type I/O: Input/Output
Type PD or PU: Internal Pulldown or Pullup
Type S: Strap Configuration Pin