JAJSD08B October   2015  – March 2017 DP83867CS , DP83867E , DP83867IS

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      システム図
  4. 改訂履歴
  5. Device Comparison
  6. Pin Configuration and Functions
    1.     Pin Functions
    2. 6.1 Unused Pins
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Power-Up Timing
    7. 7.7  Reset Timing
    8. 7.8  MII Serial Management Timing
    9. 7.9  SGMII Timing
    10. 7.10 RGMII Timing
    11. 7.11 DP83867E Start of Frame Detection Timing
    12. 7.12 DP83867IS/CS Start of Frame Detection Timing
    13. 7.13 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 WoL (Wake-on-LAN) Packet Detection
        1. 8.3.1.1 Magic Packet Structure
        2. 8.3.1.2 Magic Packet Example
        3. 8.3.1.3 Wake-on-LAN Configuration and Status
      2. 8.3.2 Start of Frame Detect for IEEE 1588 Time Stamp
        1. 8.3.2.1 SFD Latency Variation and Determinism
          1. 8.3.2.1.1 1000-Mb SFD Variation in Master Mode
          2. 8.3.2.1.2 1000-Mb SFD Variation in Slave Mode
          3. 8.3.2.1.3 100-Mb SFD Variation
      3. 8.3.3 Clock Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 MAC Interfaces
        1. 8.4.1.1 Serial GMII (SGMII)
        2. 8.4.1.2 Reduced GMII (RGMII)
          1. 8.4.1.2.1 1000-Mbps Mode Operation
          2. 8.4.1.2.2 1000-Mbps Mode Timing
          3. 8.4.1.2.3 10- and 100-Mbps Mode
      2. 8.4.2 Serial Management Interface
        1. 8.4.2.1 Extended Address Space Access
          1. 8.4.2.1.1 Write Address Operation
          2. 8.4.2.1.2 Read Address Operation
          3. 8.4.2.1.3 Write (No Post Increment) Operation
          4. 8.4.2.1.4 Read (No Post Increment) Operation
          5. 8.4.2.1.5 Write (Post Increment) Operation
          6. 8.4.2.1.6 Read (Post Increment) Operation
          7. 8.4.2.1.7 Example of Read Operation Using Indirect Register Access
          8. 8.4.2.1.8 Example of Write Operation Using Indirect Register Access
      3. 8.4.3 Auto-Negotiation
        1. 8.4.3.1 Speed and Duplex Selection - Priority Resolution
        2. 8.4.3.2 Master and Slave Resolution
        3. 8.4.3.3 Pause and Asymmetrical Pause Resolution
        4. 8.4.3.4 Next Page Support
        5. 8.4.3.5 Parallel Detection
        6. 8.4.3.6 Restart Auto-Negotiation
        7. 8.4.3.7 Enabling Auto-Negotiation Through Software
        8. 8.4.3.8 Auto-Negotiation Complete Time
        9. 8.4.3.9 Auto-MDIX Resolution
      4. 8.4.4 Loopback Mode
        1. 8.4.4.1 Near-End Loopback
          1. 8.4.4.1.1 MII Loopback
          2. 8.4.4.1.2 PCS Loopback
          3. 8.4.4.1.3 Digital Loopback
          4. 8.4.4.1.4 Analog Loopback
        2. 8.4.4.2 External Loopback
        3. 8.4.4.3 Far-End (Reverse) Loopback
      5. 8.4.5 BIST Configuration
      6. 8.4.6 Cable Diagnostics
        1. 8.4.6.1 TDR
        2. 8.4.6.2 ALCD
        3. 8.4.6.3 Energy Detect
        4. 8.4.6.4 Fast Link Drop
        5. 8.4.6.5 Fast Link Detect
        6. 8.4.6.6 Speed Optimization
        7. 8.4.6.7 Mirror Mode
        8. 8.4.6.8 Interrupt
        9. 8.4.6.9 IEEE 802.3 Test Modes
    5. 8.5 Programming
      1. 8.5.1 Strap Configuration
      2. 8.5.2 LED Configuration
      3. 8.5.3 LED Operation From 1.8-V I/O VDD Supply
      4. 8.5.4 PHY Address Configuration
      5. 8.5.5 Reset Operation
        1. 8.5.5.1 Hardware Reset
        2. 8.5.5.2 IEEE Software Reset
        3. 8.5.5.3 Global Software Reset
        4. 8.5.5.4 Global Software Restart
        5. 8.5.5.5 PCS Restart
      6. 8.5.6 Power-Saving Modes
        1. 8.5.6.1 IEEE Power Down
        2. 8.5.6.2 Deep Power-Down Mode
        3. 8.5.6.3 Active Sleep
        4. 8.5.6.4 Passive Sleep
    6. 8.6 Register Maps
      1. 8.6.1  Basic Mode Control Register (BMCR)
      2. 8.6.2  Basic Mode Status Register (BMSR)
      3. 8.6.3  PHY Identifier Register #1 (PHYIDR1)
      4. 8.6.4  PHY Identifier Register #2 (PHYIDR2)
      5. 8.6.5  Auto-Negotiation Advertisement Register (ANAR)
      6. 8.6.6  Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
      7. 8.6.7  Auto-Negotiate Expansion Register (ANER)
      8. 8.6.8  Auto-Negotiation Next Page Transmit Register (ANNPTR)
      9. 8.6.9  Auto-Negotiation Next Page Receive Register (ANNPRR)
      10. 8.6.10 1000BASE-T Configuration Register (CFG1)
      11. 8.6.11 Status Register 1 (STS1)
      12. 8.6.12 Extended Register Addressing
        1. 8.6.12.1 Register Control Register (REGCR)
        2. 8.6.12.2 Address or Data Register (ADDAR)
      13. 8.6.13 1000BASE-T Status Register (1KSCR)
      14. 8.6.14 PHY Control Register (PHYCR)
      15. 8.6.15 PHY Status Register (PHYSTS)
      16. 8.6.16 MII Interrupt Control Register (MICR)
      17. 8.6.17 Interrupt Status Register (ISR)
      18. 8.6.18 Configuration Register 2 (CFG2)
      19. 8.6.19 Receiver Error Counter Register (RECR)
      20. 8.6.20 BIST Control Register (BISCR)
      21. 8.6.21 Status Register 2 (STS2)
      22. 8.6.22 LED Configuration Register 1 (LEDCR1)
      23. 8.6.23 LED Configuration Register 2 (LEDCR2)
      24. 8.6.24 LED Configuration Register (LEDCR3)
      25. 8.6.25 Configuration Register 3 (CFG3)
      26. 8.6.26 Control Register (CTRL)
      27. 8.6.27 Testmode Channel Control (TMCH_CTRL)
      28. 8.6.28 Fast Link Drop Configuration Register (FLD_CFG)
      29. 8.6.29 Configuration Register 4 (CFG4)
      30. 8.6.30 RGMII Control Register (RGMIICTL)
      31. 8.6.31 RGMII Control Register 2 (RGMIICTL2)
      32. 8.6.32 SGMII Auto-Negotiation Status (SGMII_ANEG_STS)
      33. 8.6.33 100BASE-TX Configuration (100CR)
      34. 8.6.34 Skew FIFO Status (SKEW_FIFO)
      35. 8.6.35 Strap Configuration Status Register 1 (STRAP_STS1)
      36. 8.6.36 Strap Configuration Status Register 2 (STRAP_STS2)
      37. 8.6.37 BIST Control and Status Register 1 (BICSR1)
      38. 8.6.38 BIST Control and Status Register 2 (BICSR2)
      39. 8.6.39 RGMII Delay Control Register (RGMIIDCTL)
      40. 8.6.40 SGMII Control Register 1 (SGMIICTL1)
      41. 8.6.41 Sync FIFO Control (SYNC_FIFO_CTRL)
      42. 8.6.42 Loopback Configuration Register (LOOPCR)
      43. 8.6.43 Receive Configuration Register (RXFCFG)
      44. 8.6.44 Receive Status Register (RXFSTS)
      45. 8.6.45 Pattern Match Data Register 1 (RXFPMD1)
      46. 8.6.46 Pattern Match Data Register 2 (RXFPMD2)
      47. 8.6.47 Pattern Match Data Register 3 (RXFPMD3)
      48. 8.6.48 SecureOn Pass Register 2 (RXFSOP1)
      49. 8.6.49 SecureOn Pass Register 2 (RXFSOP2)
      50. 8.6.50 SecureOn Pass Register 3 (RXFSOP3)
      51. 8.6.51 Receive Pattern Register 1 (RXFPAT1)
      52. 8.6.52 Receive Pattern Register 2 (RXFPAT2)
      53. 8.6.53 Receive Pattern Register 3 (RXFPAT3)
      54. 8.6.54 Receive Pattern Register 4 (RXFPAT4)
      55. 8.6.55 Receive Pattern Register 5 (RXFPAT5)
      56. 8.6.56 Receive Pattern Register 6 (RXFPAT6)
      57. 8.6.57 Receive Pattern Register 7 (RXFPAT7)
      58. 8.6.58 Receive Pattern Register 8 (RXFPAT8)
      59. 8.6.59 Receive Pattern Register 9 (RXFPAT9)
      60. 8.6.60 Receive Pattern Register 10 (RXFPAT10)
      61. 8.6.61 Receive Pattern Register 11 (RXFPAT11)
      62. 8.6.62 Receive Pattern Register 12 (RXFPAT12)
      63. 8.6.63 Receive Pattern Register 13 (RXFPAT13)
      64. 8.6.64 Receive Pattern Register 14 (RXFPAT14)
      65. 8.6.65 Receive Pattern Register 15 (RXFPAT15)
      66. 8.6.66 Receive Pattern Register 16 (RXFPAT16)
      67. 8.6.67 Receive Pattern Register 17 (RXFPAT17)
      68. 8.6.68 Receive Pattern Register 18 (RXFPAT18)
      69. 8.6.69 Receive Pattern Register 19 (RXFPAT19)
      70. 8.6.70 Receive Pattern Register 20 (RXFPAT20)
      71. 8.6.71 Receive Pattern Register 21 (RXFPAT21)
      72. 8.6.72 Receive Pattern Register 22 (RXFPAT22)
      73. 8.6.73 Receive Pattern Register 23 (RXFPAT23)
      74. 8.6.74 Receive Pattern Register 24 (RXFPAT24)
      75. 8.6.75 Receive Pattern Register 25 (RXFPAT25)
      76. 8.6.76 Receive Pattern Register 26 (RXFPAT26)
      77. 8.6.77 Receive Pattern Register 27 (RXFPAT27)
      78. 8.6.78 Receive Pattern Register 28 (RXFPAT28)
      79. 8.6.79 Receive Pattern Register 29 (RXFPAT29)
      80. 8.6.80 Receive Pattern Register 30 (RXFPAT30)
      81. 8.6.81 Receive Pattern Register 31 (RXFPAT31)
      82. 8.6.82 Receive Pattern Register 32 (RXFPAT32)
      83. 8.6.83 Receive Pattern Byte Mask Register 1 (RXFPBM1)
      84. 8.6.84 Receive Pattern Byte Mask Register 2 (RXFPBM2)
      85. 8.6.85 Receive Pattern Byte Mask Register 3 (RXFPBM3)
      86. 8.6.86 Receive Pattern Byte Mask Register 4 (RXFPBM4)
      87. 8.6.87 Receive Pattern Control (RXFPATC)
      88. 8.6.88 10M SGMII Configuration (10M_SGMII_CFG)
      89. 8.6.89 I/O Configuration (IO_MUX_CFG)
      90. 8.6.90 GPIO Mux Control Register (GPIO_MUX_CTRL)
      91. 8.6.91 TDR General Configuration Register 1 (TDR_GEN_CFG1)
      92. 8.6.92 Advanced Link Cable Diagnostics Control Register (ALCD_CTRL)
      93. 8.6.93 MMD3 PCS Control Register (MMD3_PCS_CTRL)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Cable Line Driver
        2. 9.2.1.2 Clock In (XI) Recommendation
        3. 9.2.1.3 Crystal Recommendations
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 MAC Interface
          1. 9.2.2.1.1 SGMII Layout Guidelines
          2. 9.2.2.1.2 RGMII Layout Guidelines
        2. 9.2.2.2 Media Dependent Interface (MDI)
          1. 9.2.2.2.1 MDI Layout Guidelines
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Signal Traces
      2. 11.1.2 Return Path
      3. 11.1.3 Transformer Layout
      4. 11.1.4 Metal Pour
      5. 11.1.5 PCB Layer Stacking
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

特長

  • 非常に短いレイテンシ: TX < 90ns、RX < 290ns
  • 低消費電力: 457mW
  • IEC 61000-4-2で8000Vを超えるESD保護
  • EN55011 Class Bの放射基準に合致
  • RX/TXで16のRGMII遅延モードをプログラム可能
  • MDI終端抵抗を内蔵
  • MACインターフェイスの終端インピーダンスをプログラム可能
  • WoL (Wake-on-LAN) パケット検出
  • 25MHzまたは125MHzの同期クロック出力
  • IEEE 1588タイム・スタンプのサポート
  • RJ45ミラー・モード
  • IEEE 802.3 10BASE-Te、100BASE-TX、1000BASE-T仕様と完全互換
  • ケーブル診断
  • RGMIIおよびSGMII MACインターフェイス・オプション
  • I/O電圧を構成可能(3.3V、2.5V、1.8V)
  • 高速なリンク・アップ/リンク・ドロップ・モード
  • JTAGのサポート