JAJSI42D March   2016  – October 2019 DS250DF410

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements, Retimer Jitter Specifications
    7. 7.7  Timing Requirements, Retimer Specifications
    8. 7.8  Timing Requirements, Recommended Calibration Clock Specifications
    9. 7.9  Recommended SMBus Switching Characteristics (Slave Mode)
    10. 7.10 Recommended SMBus Switching Characteristics (Master Mode)
    11. 7.11 Recommended JTAG Switching Characteristics
    12. 7.12 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Data Path Operation
      2. 8.3.2  Signal Detect
      3. 8.3.3  Continuous Time Linear Equalizer (CTLE)
      4. 8.3.4  Variable Gain Amplifier (VGA)
      5. 8.3.5  Cross-Point Switch
      6. 8.3.6  Decision Feedback Equalizer (DFE)
      7. 8.3.7  Clock and Data Recovery (CDR)
      8. 8.3.8  Calibration Clock
      9. 8.3.9  Differential Driver with FIR Filter
        1. 8.3.9.1 Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization
        2. 8.3.9.2 Output Driver Polarity Inversion
      10. 8.3.10 Debug Features
        1. 8.3.10.1 Pattern Generator
        2. 8.3.10.2 Pattern Checker
        3. 8.3.10.3 Eye Opening Monitor
      11. 8.3.11 Interrupt Signals
      12. 8.3.12 JTAG Boundary Scan
    4. 8.4 Device Functional Modes
      1. 8.4.1 Supported Data Rates
      2. 8.4.2 SMBus Master Mode
      3. 8.4.3 Device SMBus Address
    5. 8.5 Programming
      1. 8.5.1 Bit Fields in the Register Set
      2. 8.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Front-Port Jitter Cleaning Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Active Cable Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Backplane and Mid-plane Applications
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

ABM Package
101-Pin FC/CSP
Top View
DS250DF410 pinout_jtag_DS250F410_snls456.png

Pin Functions

PIN TYPE INTERNAL
PULL-UP/
PULL-DOWN		 DESCRIPTION
NAME NO.
HIGH SPEED DIFFERENTIAL I/Os
RX0N A10 Input None Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs need to be AC coupled.(1)
RX0P A11 Input None
RX1N A7 Input None Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs need to be AC coupled.(1)
RX1P A8 Input None
RX2N A4 Input None Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs need to be AC coupled.(1)
RX2P A5 Input None
RX3N A1 Input None Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs need to be AC coupled.(1)
RX3P A2 Input None
TX0N L10 Output None Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. These outputs need to be AC coupled.(1)
TX0P L11 Output None
TX1N L7 Output None Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. These outputs need to be AC coupled.(1)
TX1P L8 Output None
TX2N L4 Output None Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. These outputs need to be AC coupled.(1)
TX2P L5 Output None
TX3N L1 Output None Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. These outputs need to be AC coupled.(1)
TX3P L2 Output None
CALIBRATION CLOCK PINS
CAL_CLK_IN/
JTAG_TDI		 F1 Input, 2.5V CMOS Weak pull-up in JTAG mode. Weak pull-down in functional mode 25 MHz (±100 PPM) 2.5-V single-ended clock from external oscillator. No stringent phase noise or jitter requirements on this clock. Used to calibrate VCO frequency range.

In JTAG mode (EN_SMB = 1 kΩ to GND), this is JTAG Test Data In (TDI).
CAL_CLK_OUT/
JTAG_TDO		 F11 Output, 2.5V CMOS None 2.5-V buffered replica of calibration clock input (pin E1) for connecting multiple devices in a daisy-chained fashion.

In JTAG mode (EN_SMB = 1 kΩ to GND), this is JTAG Test Data Out (TDO).
SYSTEM MANAGEMENT BUS (SMBus) PINS
ADDR0 D11 Input, 4-level None 4-level strap pins used to set the SMBus address of the device. The pin state is read on power-up. The multi-level nature of these pins allows for 16 unique device addresses. The four strap options include:
0: 1 kΩ to GND
R: 20 kΩ to GND
F: Float
1: 1 kΩ to VDD
Refer to Device SMBus Address for more information.
In JTAG mode (EN_SMB = 1 kΩ to GND), ADDR1 is JTAG Test Reset (TRS).
ADDR1/JTAG_TRS D1 Input, 4-level Weak pull-up in JTAG mode
EN_SMB G1 Input, 4-level None Four-level 2.5-V input used to select between SMBus master mode (float) and SMBus slave mode (high). The four defined levels are:
0: 1 kΩ to GND - JTAG mode; certain pins take on JTAG functionality
R: 20 kΩ to GND - RESERVED, TI test mode
F: Float - SMBus Master Mode
1: 1 kΩ to VDD - SMBus Slave Mode
SDA G11 I/O, 3.3V LVCMOS, Open Drain None SMBus data input / open drain output. External 2-kΩ to 5-kΩ pull-up resistor is required as per SMBus interface standard. This pin is 3.3V-tolerant.
SDC H11 I/O, 3.3V LVCMOS, Open Drain None SMBus clock input / open drain clock output. External 2-kΩ to 5-kΩ pull-up resistor is required as per SMBus interface standard. This pin is 3.3V-tolerant.
SMBus MASTER MODE PINS
ALL_DONE_N E1 Output, LVCMOS None Indicates the completion of a valid EEPROM register load operation when in SMBus Master Mode (EN_SMB=Float):
High = External EEPROM load failed or incomplete
Low = External EEPROM load successful and complete
When in SMBus slave mode (EN_SMB=1), this output reflects the status of the READ_EN_N input.
READ_EN_N E11 Input, 3.3V LVCMOS Weak pull-up SMBus Master Mode (EN_SMB=Float): When asserted low, initiates the SMBus master mode EEPROM read function. Once EEPROM read is complete (indicated by assertion of ALL_DONE_N low), this pin can be held low for normal device operation.

SMBus Slave Mode (EN_SMB=1): When asserted low, this causes the device to be held in reset (SMBus state machine reset and register reset). This pin should be pulled high or left floating for normal operation in SMBus Slave Mode.
This pin is 3.3V-tolerant.
MISCELLANEOUS PINS
INT_N H1 Output, LVCMOS, Open Drain None Open-drain 3.3-V tolerant active-low interrupt output. This pin is pulled low when an interrupt occurs. The events which trigger an interrupt are programmable through SMBus registers. INT_N can be connected in a wired-OR fashion with other device's interrupt pin. A single pull-up resistor in the 2-kΩ to 5-kΩ range is adequate for the entire INT_N net.
TEST0/JTAG_TCK D10 Input, LVCMOS No pull-up in JTAG mode. Weak pull-up in functional mode. Reserved TI test pins. During normal (non-test-mode) operation, these pins are configured as inputs and therefore they are not affected by the presence of a signal. These pins may be left floating, tied to GND, or connected to a 2.5-V (max) output.

In JTAG mode (EN_SMB = 1 kΩ to GND), TEST0 is JTAG Test Clock (TCK) and TEST1 is JTAG Test Mode Select (TMS).
TEST1/JTAG_TMS D2 Input, LVCMOS Weak pull-up
TEST2 E10 Input, LVCMOS Weak pull-up Reserved TI test pins. During normal (non-test-mode) operation, these pins are configured as inputs and therefore they are not affected by the presence of a signal. These pins may be left floating, tied to GND, or connected to a 2.5-V (max) output.
TEST3 E2 Input, LVCMOS Weak pull-up
TEST4 H10 Input, LVCMOS Weak pull-up
TEST5 H2 Input, LVCMOS Weak pull-up
POWER
GND A3, A6, A9, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, C1, C6, C11, D6, E3, E5, E7, E9, F3, F4, F5, F6, F7, F8, F9, G2, G3, G5, G7, G9, G10, H6, J1, J6, J11, K1, K2, K3, K4, K5, K6, K7, K8, K9, K10, K11, L3, L6, L9 Power None Ground reference. The GND pins on this device should be connected through a low-resistance path to the board GND plane.
VDD C3, C9, D3, D4, D5, D7, D8, D9, H3, H4, H5, H7, H8, H9, J3, J9 Power None Power supply, VDD = 2.5 V ±5%. TI recommends connecting at least six de-coupling capacitors between the DS250DF410’s VDD plane and GND as close to the DS250DF410 as possible. For example, four 0.1-μF capacitors and two 1-μF capacitors directly beneath the device or as close to the VDD pins as possible. The VDD pins on this device should be connected through a low-resistance path to the board VDD plane.
(1) High-speed pins do not have short-circuit protection. High-speed pins should be AC-coupled.