SLOS580G May   2008  – March 2015 ISO15 , ISO35

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Simplified Schematics
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Dissipation Ratings
    6. 7.6  Supply Current
    7. 7.7  Driver Electrical Characteristics
    8. 7.8  Receiver Electrical Characteristics
    9. 7.9  Driver Switching Characteristics
    10. 7.10 Receiver Switching Characteristics
    11. 7.11 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Insulation and Safety-Related Package Characteristics
      2. 9.3.2 IEC 60664-1 Ratings Table
      3. 9.3.3 Regulatory Information
      4. 9.3.4 Safety-Limiting Values
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device I/O Schematics
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

9 Detailed Description

9.1 Overview

The ISO15 and ISO15M are isolated half-duplex differential line drivers and receivers while the ISO35 and ISO35M are isolated full-duplex differential line transceivers for TIA/EIA 485/422 applications. They are rated to provide galvanic isolation of up to 2500 Vrms for 60 sec as per the standard. They have active-high driver enables and active-low receiver enables to control the data flow.

When the driver enable pin, DE, is logic high, the differential outputs Y and Z follow the logic states at data input D. A logic high at D causes Y to turn high and Z to turn low. In this case the differential output voltage defined as VOD = V(Y) – V(Z) is positive. When D is low, the output states reverse, Z turns high, Y becomes low, and VOD is negative. When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin has an internal pulldown resistor to ground, thus when left open the driver is disabled (high-impedance) by default. The D pin has an internal pullup resistor to VCC, thus, when left open while the driver is enabled, output Y turns high and Z turns low.

When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage defined as VID = V(A) – V(B) is positive and higher than the positive input threshold, VIT+, the receiver output, R, turns high. When VID is negative and less than the negative and lower than the negative input threshold, VIT– , the receiver output, R, turns low. If VID is between VIT+ and VIT– the output is indeterminate. When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven (idle bus).

9.2 Functional Block Diagrams

ISO15 ISO35 ISO15M ISO35M functional_diagram2_los581.gif
ISO15 ISO35 ISO15M ISO35M functional_diagram1_los581.gif

9.3 Feature Description

9.3.1 Insulation and Safety-Related Package Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
L(I01) Minimum air gap (Clearance)(1) Shortest terminal to terminal distance through air 8.34 mm
L(I02) Minimum external tracking (Creepage)(1) Shortest terminal to terminal distance across the package surface 8.1 mm
CTI Tracking resistance (Comparative Tracking Index) DIN IEC 60112 / VDE 0303 Part 1 ≥400 V
DTI Minimum Internal Gap (Internal Clearance) Distance through the insulation 0.008 mm
RIO Isolation resistance Input to output, VIO = 500 V, TA = 25°C, all pins on each side of the barrier tied together creating a two-terminal device >1012 Ω
CIO Barrier capacitance input to output VI = 0.4 sin (4E6πt) 2 pF
CI Input capacitance to ground VI = 0.4 sin (4E6πt) 2 pF
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance. Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.

DIN V VDE V 0884-10 Insulation Characteristics

over recommended operating conditions (unless otherwise noted)(1)

PARAMETER TEST CONDITIONS SPECIFICATION UNIT
VIOTM Transient overvoltage Method a, t = 60 s, Qualification test 4000 VPK
VIORM Maximum working insulation voltage 560 VPK
VPR Input to output test voltage Method b1, VPR = VIORM × 1.875,
100% Production test with t = 1 s, Partial discharge < 5 pC
1050 VPK
RS Insulation resistance VIO = 500 V at TS >109 Ω
Pollution degree 2
(1) Climatic Classification 40/125/21

9.3.2 IEC 60664-1 Ratings Table

PARAMETER TEST CONDITIONS SPECIFICATION
Basic isolation group Material group II
Installation classification Rated mains voltage ≤ 150 VRMS I-IV
Rated mains voltage ≤ 300 VRMS I-III
Rated mains voltage ≤ 400 VRMS I-II

9.3.3 Regulatory Information

VDE CSA UL
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Approved under CSA Component Acceptance Notice 5A and IEC 60950-1 Recognized under UL 1577 Component Recognition Program(1)
Basic insulation,
4000 VPK Maximum transient overvoltage,
560 VPK Maximum working voltage
2500 VRMS Isolation rating,
396 VPK Basic working voltage per CSA 60950-1-07 and IEC 60950-1 (2nd Ed)
Single Protection, 2500 VRMS
Certificate number: 40016131 Master contract number: 220991 File number: E181974
(1) Production tested ≥3000 VRMS for 1 second in accordance with UL 1577.

9.3.4 Safety-Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures.

PARAMETER MIN TYP MAX UNIT
IS Safety input, output, or supply current DW-16 θJA = 168 °C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C 240 mA
TS Maximum case temperature DW-16 150 °C

The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in Thermal Information is that of a device installed in a Low-Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

ISO15 ISO35 ISO15M ISO35M thermalgraph1.gifFigure 16. DW-16 θJC Thermal Derating Curve per VDE

9.4 Device Functional Modes

Table 1. Driver Function Table(2)

VCC1 VCC2 INPUT
(D)
ENABLE INPUT
(DE)
OUTPUTS(1)
Y / A Z / B
PU PU H H H L
PU PU L H L H
PU PU X L Hi-Z Hi-Z
PU PU X OPEN Hi-Z Hi-Z
PU PU OPEN H H L
PD PU X X Hi-Z Hi-Z
PU PD X X Hi-Z Hi-Z
PD PD X X Hi-Z Hi-Z
(1) Driver output pins are Y and Z for full-duplex devices and A & B for half-duplex devices.
(2) PU = Powered Up; PD = Powered Down; H = Logic High; L= Logic Low; X = Irrelevant, Hi-Z = High Impedance (off)

Table 2. Receiver Function Table(1)

VCC1 VCC2 DIFFERENTIAL INPUT
VID = (VA – VB)
ENABLE
(RE)
OUTPUT
(R)
PU PU –0.01 V ≤ VID L H
PU PU –0.2 V < VID < –0.01 V L ?
PU PU VID ≤ –0.2 V L L
PU PU X H Hi-Z
PU PU X OPEN Hi-Z
PU PU Open circuit L H
PU PU Short Circuit L H
PU PU Idle (terminated) bus L H
PD PU X X Hi-Z
PU PD X L H
(1) PU = Powered Up; PD = Powered Down; H = Logic High; L= Logic Low; X = Irrelevant, Hi-Z = High Impedance (off), ? = Indeterminate

9.4.1 Device I/O Schematics

ISO15 ISO35 ISO15M ISO35M eval_shm_los851.pngFigure 17. Device I/O Schematics