SLLS867K September   2007  – October 2015 ISO7230C , ISO7230M , ISO7231C , ISO7231M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: VCC1 and VCC2 at 5-V
    6. 7.6  Electrical Characteristics: VCC1 at 5-V, VCC2 at 3.3-V
    7. 7.7  Electrical Characteristics: VCC1 at 3.3-V, VCC2 at 5-V
    8. 7.8  Electrical Characteristics: VCC1 and VCC2 at 3.3 V
    9. 7.9  Power Dissipation Characteristics
    10. 7.10 Switching Characteristics: VCC1 and VCC2 at 5-V
    11. 7.11 Switching Characteristics: VCC1 at 5-V, VCC2 at 3.3-V
    12. 7.12 Switching Characteristics: VCC1 at 3.3-V and VCC2 at 5-V
    13. 7.13 Switching Characteristics: VCC1 and VCC2 at 3.3-V
    14. 7.14 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Package Insulation and Safety-Related Specifications
      2. 9.3.2 Insulation Characteristics
      3. 9.3.3 Regulatory Information
      4. 9.3.4 Safety Limiting Values
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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7 Specifications

7.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
VCC Supply voltage(2), VCC1, VCC2 –0.5 6 V
VI Voltage at INx, OUTx, ENx –0.5 VCC + 0.5(3) V
IO Output current –15 15 mA
TJ Maximum junction temperature 170 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal and are peak voltage values.
(3) Maximum voltage must not exceed 6 V.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
Machine model (MM), ANSI/ESDS5.2-1996 ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC1, VCC2 Supply voltage - 3.3-V Operation 3.15 5.5 V
Supply voltage - 5-V Operation
IOH High-level output current –4 mA
IOL Low-level output current 4 mA
tui Input pulse width ISO723xC 40 ns
ISO723xM 6.67 5
1/tui Signaling rate ISO723xC 0 30(1) 25 Mbps
ISO723xM 0 200(1) 150
VIH High-level input voltage (IN) ISO723xM 0.7 VCC VCC V
VIL Low-level input voltage (IN) 0 0.3 VCC
VIH High-level input voltage (IN) (EN on all devices) ISO723xC 2 5.5 V
VIL Low-level input voltage (IN) (EN on all devices) 0 0.8
TA Ambient temperature -40 25 125 °C
TJ Junction temperature 150 °C
H External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9 1000 A/m
(1) Typical sigalling rate under ideal conditions at 25°C.

7.4 Thermal Information

THERMAL METRIC(1) ISO7230C, ISO7230M
ISO7231C, ISO7231M		 UNIT
DW (SOIC)
16 PINS
RθJA Junction-to-ambient thermal resistance 168 °C/W
77.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 39.5 °C/W
RθJB Junction-to-board thermal resistance 41.9 °C/W
ψJT Junction-to-top characterization parameter 13.5 °C/W
ψJB Junction-to-board characterization parameter 41.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics: VCC1 and VCC2 at 5-V(1)

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
ICC1 ISO7230C/M Quiescent VI = VCCI or 0 V, all channels, no load,
EN at 3 V		 1 3 mA
25 Mbps 7 9.5
ISO7231C/M Quiescent VI = VCCI or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V 		6.5 11 mA
25 Mbps 11 17
ICC2 ISO7230C/M Quiescent VI = VCCI or 0 V, all channels, no load,
EN at 3 V		 15 22 mA
25 Mbps 17 24
ISO7231C/M Quiescent VI = VCCI or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V 		13 20 mA
25 Mbps 17.5 27
ELECTRICAL CHARACTERISTICS
IOFF Sleep mode output current ENx at 0 V, single channel 0 μA
VOH High-level output voltage IOH = –4 mA, See Figure 8 VCCO – 0.8 V
IOH = –20 μA, See Figure 8 VCCO – 0.1
VOL Low-level output voltage IOL = 4 mA, See Figure 8 0.4 V
IOL = 20 μA, See Figure 8 0.1
VI(HYS) Input voltage hysteresis 150 mV
IIH High-level input current INx at VCCI 10 μA
IIL Low-level input current INx at 0 V –10
CI Input capacitance to ground INx at VCCI, VI = 0.4 sin (4E6πt) 2 pF
CMTI Common-mode transient immunity VI = VCCI or 0 V, See Figure 11 25 50 kV/μs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3.3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.

7.6 Electrical Characteristics: VCC1 at 5-V, VCC2 at 3.3-V(1)

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
ICC1 ISO7230C/M Quiescent VI = VCCI or 0 V, all channels, no load, EN at 3 V 1 3 mA
25 Mbps 7 9.5
ISO7231C/M Quiescent VI = VCCI or 0 V, all channels, no load, EN1 at 3 V,
EN2 at 3 V 		6.5 11 mA
25 Mbps 11 17
ICC2 ISO7230C/M Quiescent VI = VCCI or 0 V, all channels, no load, EN at 3 V 9 15 mA
25 Mbps 10 17
ISO7231C/M Quiescent VI = VCCI or 0 V, all channels, no load, EN1 at 3 V,
EN2 at 3 V 		8 12 mA
25 Mbps 10.5 16
ELECTRICAL CHARACTERISTICS
IOFF Sleep mode output current ENx at 0 V, Single channel 0 μA
VOH High-level output voltage IOH = –4 mA, See Figure 8 ISO7230 VCCO – 0.4 V
ISO7231
(5-V side)		 VCCO – 0.8
IOH = –20 μA, See Figure 8 VCCO – 0.1
VOL Low-level output voltage IOL = 4 mA, See Figure 8 0.4 V
IOL = 20 μA, See Figure 8 0.1
VI(HYS) Input voltage hysteresis 150 mV
IIH High-level input current INx at VCCI 10 μA
IIL Low-level input current INx at 0 V –10
CI Input capacitance to ground INx at VCCI, VI = 0.4 sin (4E6πt) 2 pF
CMTI Common-mode transient immunity VI = VCCI or 0 V, See Figure 11 25 50 kV/μs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3.3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.

7.7 Electrical Characteristics: VCC1 at 3.3-V, VCC2 at 5-V(1)

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
ICC1 ISO7230C/M Quiescent VI = VCCI or 0 V, all channels, no load, EN at 3 V 0.5 1 mA
25 Mbps 3 5
ISO7231C/M Quiescent VI = VCCI or 0 V, all channels, no load, EN1 at 3 V,
EN2 at 3 V 		4.5 7 mA
25 Mbps 6.5 11
ICC2 ISO7230C/M Quiescent VI = VCCI or 0 V, all channels, no load, EN at 3 V 15 22 mA
25 Mbps 17 24
ISO7231C/M Quiescent VI = VCCI or 0 V, all channels, no load, EN1 at 3 V,
EN2 at 3 V 		13 20 mA
25 Mbps 17.5 27
ELECTRICAL CHARACTERISTICS
IOFF Sleep mode output current ENx at 0 V, Single channel 0 μA
VOH High-level output voltage IOH = –4 mA, See Figure 8 ISO7230 VCCO – 0.4 V
ISO7231
(5-V side)		 VCCO – 0.8
IOH = –20 μA, See Figure 8 VCCO – 0.1
VOL Low-level output voltage IOL = 4 mA, See Figure 8 0.4 V
IOL = 20 μA, See Figure 8 0.1
VI(HYS) Input voltage hysteresis 150 mV
IIH High-level input current INx at VCCI 10 μA
IIL Low-level input current INx at 0 V –10
CI Input capacitance to ground INx at VCCI, VI = 0.4 sin (4E6πt) 2 pF
CMTI Common-mode transient immunity VI = VCCI or 0 V, See Figure 11 25 50 kV/μs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3.3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.

7.8 Electrical Characteristics: VCC1 and VCC2 at 3.3 V(1)

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
ICC1 ISO7230C/M Quiescent VI = VCCI or 0 V, all channels, no load,
EN at 3 V		 0.5 1 mA
25 Mbps 3 5
ISO7231C/M Quiescent VI = VCCI or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V 		4.5 7 mA
25 Mbps 6.5 11
ICC2 ISO7230C/M Quiescent VI = VCCI or 0 V, all channels, no load,
EN at 3 V		 9 15 mA
25 Mbps 10 17
ISO7231C/M Quiescent VI = VCCI or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V 		8 12 mA
25 Mbps 10.5 16
ELECTRICAL CHARACTERISTICS
IOFF Sleep mode output current ENx at 0 V, single channel 0 μA
VOH High-level output voltage IOH = –4 mA, See Figure 8 VCCO – 0.4 V
IOH = –20 μA, See Figure 8 VCCO – 0.1
VOL Low-level output voltage IOL = 4 mA, See Figure 8 0.4 V
IOL = 20 μA, See Figure 8 0.1
VI(HYS) Input voltage hysteresis 150 mV
IIH High-level input current INx at VCCI 10 μA
IIL Low-level input current INx at 0 V –10
CI Input capacitance to ground INx at VCCI, VI = 0.4 sin (4E6πt) 2 pF
CMTI Common-mode transient immunity VI = VCCI or 0 V, See Figure 11 25 50 kV/μs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3.3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.

7.9 Power Dissipation Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER ISO7230C, ISO7230M, ISO7231C, ISO7231M UNIT
DW (SOIC)
16 PINS
PD Device power dissipation, VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, D Input a 50% duty cycle square wave 220 mW

7.10 Switching Characteristics: VCC1 and VCC2 at 5-V

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay ISO723xC See Figure 8 18 42 ns
PWD Pulse-width distortion(1) |tPHL – tPLH| 2.5
tPLH, tPHL Propagation delay ISO723xM 10 23 ns
PWD Pulse-width distortion(1) |tPHL – tPLH| 1 2
tsk(pp) Part-to-part skew (2) ISO723xC 8 ns
ISO723xM 0 3
tsk(o) Channel-to-channel output skew (3) ISO723xC 0 2 ns
ISO723xM 0 1
tr Output signal rise time See Figure 8 2 ns
tf Output signal fall time 2
tPHZ Propagation delay, high-level-to-high-impedance output See Figure 9 15 20 ns
tPZH Propagation delay, high-impedance-to-high-level output 15 20
tPLZ Propagation delay, low-level-to-high-impedance output 15 20
tPZL Propagation delay, high-impedance-to-low-level output 15 20
tfs Failsafe output delay time from input power loss See Figure 10 12 μs
tjit(pp) Peak-to-peak eye-pattern jitter ISO723xM 150 Mbps PRBS NRZ data input, Same polarity inputon all channels, See Figure 12 1 ns
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads.

7.11 Switching Characteristics: VCC1 at 5-V, VCC2 at 3.3-V

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay, low-to-high-level output ISO723xC See Figure 8 20 50 ns
PWD Pulse-width distortion(1) |tPHL – tPLH| 3
tPLH, tPHL Propagation delay, low-to-high-level output ISO723xM 12 29 ns
PWD Pulse-width distortion(1) |tPHL – tPLH| 1 2
tsk(pp) Part-to-part skew (2) ISO723xC 10 ns
ISO723xM 0 5
tsk(o) Channel-to-channel output skew (3) ISO723xC 0 2.5 ns
ISO723xM 0 1
tr Output signal rise time See Figure 8 2 ns
tf Output signal fall time 2
tPHZ Propagation delay, high-level-to-high-impedance output See Figure 9 15 20 ns
tPZH Propagation delay, high-impedance-to-high-level output 15 20
tPLZ Propagation delay, low-level-to-high-impedance output 15 20
tPZL Propagation delay, high-impedance-to-low-level output 15 20
tfs Failsafe output delay time from input power loss See Figure 10 18 μs
tjit(pp) Peak-to-peak eye-pattern jitter ISO723xM 150 Mbps PRBS NRZ data input, Same polarity input on all channels, See Figure 12 1 ns
(1) Also known as pulse skew
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

7.12 Switching Characteristics: VCC1 at 3.3-V and VCC2 at 5-V

, over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay ISO723xC See Figure 8 22 51 ns
PWD Pulse-width distortion(1) |tPHL – tPLH| 3
tPLH, tPHL Propagation delay ISO723xM 12 30
PWD Pulse-width distortion(1) |tPHL – tPLH| 1 2
tsk(pp) Part-to-part skew (2) ISO723xC 10 ns
ISO723xM 0 5
tsk(o) Channel-to-channel output skew (3) ISO723xC 0 2.5 ns
ISO723xM 0 1
tr Output signal rise time See Figure 8 2 ns
tf Output signal fall time 2
tPHZ Propagation delay, high-level-to-high-impedance output See Figure 9 15 20 ns
tPZH Propagation delay, high-impedance-to-high-level output 15 20
tPLZ Propagation delay, low-level-to-high-impedance output 15 20
tPZL Propagation delay, high-impedance-to-low-level output 15 20
tfs Failsafe output delay time from input power loss See Figure 10 12 μs
tjit(pp) Peak-to-peak eye-pattern jitter ISO723xM 150 Mbps PRBS NRZ data input, Same polarity input on all channels, See Figure 12 1 ns
(1) Also known as pulse skew
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads.

7.13 Switching Characteristics: VCC1 and VCC2 at 3.3-V

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay ISO723xC See Figure 8 25 56 ns
PWD Pulse-width distortion(1) |tPHL – tPLH| 4
tpLH, tpHL Propagation delay ISO723xM 12 34 ns
PWD Pulse-width distortion(1) |tPHL – tPLH| 1 2
tsk(pp) Part-to-part skew (2) ISO723xC 10 ns
ISO723xM 0 5
tsk(o) Channel-to-channel output skew (3) ISO723xC 0 3 ns
ISO723xM 0 1
tr Output signal rise time See Figure 8 2 ns
tf Output signal fall time 2
tPHZ Propagation delay, high-level-to-high-impedance output See Figure 9 15 20 ns
tPZH Propagation delay, high-impedance-to-high-level output 15 20
tPLZ Propagation delay, low-level-to-high-impedance output 15 20
tPZL Propagation delay, high-impedance-to-low-level output 15 20
tfs Failsafe output delay time from input power loss See Figure 10 18 μs
tjit(pp) Peak-to-peak eye-pattern jitter ISO723xM 150 Mbps PRBS NRZ data input, same polarity input on all channels, See Figure 12 1 ns
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads.

7.14 Typical Characteristics

ISO7230C ISO7230M ISO7231C ISO7231M icc_sr_lls867.gif Figure 1. ISO7230C/M RMS Supply Current vs Signaling Rate
ISO7230C ISO7230M ISO7231C ISO7231M pd_ta_lls867.gif Figure 3. Propagation Delay vs Free-Air Temperature
ISO7230C ISO7230M ISO7231C ISO7231M vcc1_ta_lls867.gif Figure 5. VCC1 Fail-Safe Threshold vs Free-Air Temperature
ISO7230C ISO7230M ISO7231C ISO7231M io2_vo_lls867.gif Figure 7. Low-Level Output Current vs Low-Level Output Voltage
ISO7230C ISO7230M ISO7231C ISO7231M icc2_sr_lls867.gif Figure 2. ISO7231C/M RMS Supply Current vs Signaling Rate
ISO7230C ISO7230M ISO7231C ISO7231M vi_ta_lls867.gif Figure 4. Input Threshold Voltage vs Free-Air Temperature
ISO7230C ISO7230M ISO7231C ISO7231M io_vo_lls867.gif Figure 6. High-Level Output Current vs High-Level Output Voltage