SLLS867K September   2007  – October 2015 ISO7230C , ISO7230M , ISO7231C , ISO7231M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: VCC1 and VCC2 at 5-V
    6. 7.6  Electrical Characteristics: VCC1 at 5-V, VCC2 at 3.3-V
    7. 7.7  Electrical Characteristics: VCC1 at 3.3-V, VCC2 at 5-V
    8. 7.8  Electrical Characteristics: VCC1 and VCC2 at 3.3 V
    9. 7.9  Power Dissipation Characteristics
    10. 7.10 Switching Characteristics: VCC1 and VCC2 at 5-V
    11. 7.11 Switching Characteristics: VCC1 at 5-V, VCC2 at 3.3-V
    12. 7.12 Switching Characteristics: VCC1 at 3.3-V and VCC2 at 5-V
    13. 7.13 Switching Characteristics: VCC1 and VCC2 at 3.3-V
    14. 7.14 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Package Insulation and Safety-Related Specifications
      2. 9.3.2 Insulation Characteristics
      3. 9.3.3 Regulatory Information
      4. 9.3.4 Safety Limiting Values
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DW|16
サーマルパッド・メカニカル・データ
発注情報

8 Parameter Measurement Information

ISO7230C ISO7230M ISO7231C ISO7231M swt_lls867.gif
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the Input Generator signal. It is not needed in actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 8. Switching Characteristic Test Circuit and Voltage Waveforms
ISO7230C ISO7230M ISO7231C ISO7231M tst_cit_wf_lls867.gif
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 9. Enable/Disable Propagation Delay Time Test Circuit and Waveform
ISO7230C ISO7230M ISO7231C ISO7231M failsafe_lls867.gif
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 10. Failsafe Delay Time Test Circuit and Voltage Waveforms
ISO7230C ISO7230M ISO7231C ISO7231M com_tran_imm_test_circ_sllsek9.gif
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 11. Common-Mode Transient Immunity Test Circuit
ISO7230C ISO7230M ISO7231C ISO7231M p_t_p_eye_lls867.gif

NOTE:

PRBS bit pattern run length is 216 – 1. Transition time is 800 ps. NRZ data input has no more than five consecutive 1s or 0s.
Figure 12. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform