SNVS005E November   1999  – December 2014 LM2664

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Circuit
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application - Voltage Inverter
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Requirements
        1. 9.2.2.1 Paralleling Devices
        2. 9.2.2.2 Cascading Devices
        3. 9.2.2.3 Combined Doubler and Inverter
        4. 9.2.2.4 Regulating VOUT
        5. 9.2.2.5 Output Capacitor Selection
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

8 Detailed Description

8.1 Overview

The LM2664 CMOS charge-pump voltage converter inverts a positive voltage in the range of 1.8 V to 5.5 V to the corresponding negative voltage of −1.8 V to −5.5 V. The LM2664 uses two low-cost capacitors to provide up to 40 mA of output current.

8.2 Functional Block Diagram

blockdiag.gif

8.3 Feature Description

The LM2664 contains four large CMOS switches which are switched in a sequence to invert the input supply voltage. Energy transfer and storage are provided by external capacitors. Figure 10 illustrates the voltage conversion scheme. When S1 and S3 are closed, C1 charges to the supply voltage V+. During this time interval, switches S2 and S4 are open. In the second time interval, S1 and S3 are open; at the same time, S2 and S4 are closed, C1 is charging C2. After a number of cycles, the voltage across C2 will be pumped to V+. Since the anode of C2 is connected to ground, the output at the cathode of C2 equals −(V+) when there is no load current. The output voltage drop when a load is added is determined by the parasitic resistance (Rds(on) of the MOSFET switches and the ESR of the capacitors) and the charge transfer loss between capacitors. Details will be discussed in the following application information section.

10003105.pngFigure 10. Voltage Inverting Principle

8.4 Device Functional Modes

8.4.1 Shutdown Mode

A shutdown (SD) pin is available to disable the device and reduce the quiescent current to 1 µA. Applying a voltage less than 20% of V+ to the SD pin will bring the device into shutdown mode. While in normal operating mode, the pin is connected to V+.