JAJSBA6M February   2000  – July 2016 LMC555

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Low-Power Dissipation
      2. 8.3.2 Various Packages and Compatibility
      3. 8.3.3 Operates in Both Astable and Monostable Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Monostable Operation
      2. 8.4.2 Astable Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Frequency Divider
      1. 9.3.1 Design Requirements
      2. 9.3.2 Application Curve
    4. 9.4 Pulse Width Modulator
      1. 9.4.1 Design Requirements
      2. 9.4.2 Application Curve
    5. 9.5 Pulse Position Modulator
      1. 9.5.1 Design Requirements
      2. 9.5.2 Application Curve
    6. 9.6 50% Duty Cycle Oscillator
      1. 9.6.1 Design Requirements
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11 Layout

11.1 Layout Guidelines

Standard PCB rules apply to routing the LMC555. The 0.1 µF in parallel with a 1-µF electrolytic capacitor should be as close as possible to the LMC555. The capacitor used for the time delay should also be placed as close to the discharge pin. A ground plane on the bottom layer can be used to provide better noise immunity and signal integrity.

11.2 Layout Example

The figure below is the basic layout for various applications.

  • C1 – based on time delay calculations
  • C2 – 0.01 µF bypass capacitor for control voltage pin
  • C3 – 0.1 µF bypass ceramic capacitor
  • C4 – 1-µF electrolytic bypass capacitor
  • R1 – based on time delay calculations
  • U1 – LMC555

LMC555 layout.gif Figure 18. PCB Layout