JAJSBA6M February   2000  – July 2016 LMC555

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Low-Power Dissipation
      2. 8.3.2 Various Packages and Compatibility
      3. 8.3.3 Operates in Both Astable and Monostable Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Monostable Operation
      2. 8.4.2 Astable Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Frequency Divider
      1. 9.3.1 Design Requirements
      2. 9.3.2 Application Curve
    4. 9.4 Pulse Width Modulator
      1. 9.4.1 Design Requirements
      2. 9.4.2 Application Curve
    5. 9.5 Pulse Position Modulator
      1. 9.5.1 Design Requirements
      2. 9.5.2 Application Curve
    6. 9.6 50% Duty Cycle Oscillator
      1. 9.6.1 Design Requirements
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

D, DGK, and P Packages
8-Pin SOIC, VSSOP, and PDIP
(Top View)
LMC555 866901.png
YPB Package
8-Pin DSBGA
(Top View)
LMC555 866909.png

Pin Functions

PIN I/O DESCRIPTION
SOIC, VSSOP, and PDIP NO. DSBGA NO. NAME
1 A3 GND O Ground reference voltage
2 B3 Trigger I Responsible for transition of the flip-flop from set to reset. The output of the timer depends on the amplitude of the external trigger pulse applied to this pin
3 C3 Output O Output driven waveform
4 C2 Reset I Negative pulse applied to this pin to disable or reset the timer. When not used for reset purposes, it should be connected to VCC to avoid false triggering
5 C1 Control Voltage I Control voltage controls the threshold and trigger levels. It determines the pulse width of the output waveform. An external voltage applied to this pin can also be used to modulate the output waveform
6 B1 Threshold I Compares the voltage applied to the terminal with a reference voltage of 2/3 Vcc. The amplitude of voltage applied to this terminal is responsible for the set state of the flip-flop.
7 A1 Discharge I Open collector output which discharges a capacitor between intervals (in phase with output). It toggles the output from high to low when voltage reaches 2/3 of the supply voltage
8 A2 V+ I Supply voltage with respect to GND