8.3.1 Low-Power Dissipation

The LMC555 offers the same capability of generating accurate time delays and frequencies as the LM555 but with much lower power dissipation. A power dissipation of less than 0.2 mW can be achieved with a 1.5-V operating supply voltage and less than 1 mW with a 5-V operating supply voltage. The use of TI’s LMCMOS process allows this low supply current and voltage capability. Reduced supply current spikes during output transitions and extremely low reset, trigger and threshold currents also provide low power dissipation advantages with the LMC555.

8.3.2 Various Packages and Compatibility

There are various packages available for use of the LMC555. In addition to the standard package (8-pin SOIC, VSSOP, and PDIP, the LMC555 is also available in a chip-sized package (8-bump DSBGA). The PDIP, SOIC, and VSSOP packages for the LMC555 are pin-for-pin compatible with the 555 series of timers (NE555/SE555/LM555) allowing flexibility in design and unnecessary modifications to PCB schematics and layouts.

8.3.3 Operates in Both Astable and Monostable Mode

The LMC555 can operate in both astable and monostable mode depending on the application requirements.

• Monostable mode: The LMC555 timer acts as a “one-shot” pulse generator. The pulse begins when the LMC555 timer receives a signal at the trigger input that falls below a 1/3 of the voltage supply. The width of the output pulse is determined by the time constant of an RC network. The output pulse ends when the voltage on the capacitor equals 2/3 of the supply voltage. The output pulse width can be extended or shortened depending on the application by adjusting the R and C values.
• Astable (free-running) mode: The LMC555 timer can operate as an oscillator and puts out a continuous stream of rectangular pulses having a specified frequency. The frequency of the pulse stream depends on the values of RA, RB, and C.

8.4.1 Monostable Operation

In this mode of operation, the timer functions as a one-shot (Figure 3). The external capacitor is initially held discharged by internal circuitry. Upon application of a negative trigger pulse of less than 1/3 V_S to the Trigger terminal, the flip-flop is set which both releases the short circuit across the capacitor and drives the output high.

Figure 3. Monostable (One-Shot)

The voltage across the capacitor then increases exponentially for a period of t_H = 1.1 R_AC, which is also the time that the output stays high, at the end of which time the voltage equals 2/3 V_S. The comparator then resets the flip-flop which in turn discharges the capacitor and drives the output to its low state. Figure 4 shows the waveforms generated in this mode of operation. Because the charge and the threshold level of the comparator are both directly proportional to supply voltage, the timing internal is independent of supply.

V_CC = 5 V       Top Trace: Input 5 V/Div.

TIME = 0.1 ms/Div.  Middle Trace: Output 5 V/Div.

R_A = 9.1 kΩ      Bottom Trace: Capacitor Voltage 2 V/Div.

C = 0.01 µF

Figure 4. Monostable Waveforms

Reset overrides Trigger, which can override threshold. Therefore the trigger pulse must be shorter than the desired t_H. The minimum pulse width for the Trigger is 20 ns, and it is 400 ns for the Reset. During the timing cycle when the output is high, the further application of a trigger pulse will not effect the circuit so long as the trigger input is returned high at least 10 µs before the end of the timing interval. However the circuit can be reset during this time by the application of a negative pulse to the reset terminal. The output will then remain in the low state until a trigger pulse is again applied.

When the reset function is not use, it is recommended that it be connected to V₊ to avoid any possibility of false triggering. Figure 5 is a nomograph for easy determination of RC values for various time delays.

Figure 5. Time Delay

8.4.2 Astable Operation

If the circuit is connected as shown in Figure 6 (Trigger and Threshold terminals connected together) it will trigger itself and free run as a multivibrator. The external capacitor charges through R_A + R_B and discharges through R_B. Thus the duty cycle may be precisely set by the ratio of these two resistors.

Figure 6. Astable (Variable Duty Cycle Oscillator)

In this mode of operation, the capacitor charges and discharges between 1/3 V_S and 2/3 V_S. As in the triggered mode, the charge and discharge times, and therefore the frequency are independent of the supply voltage.

Figure 7 shows the waveform generated in this mode of operation.

V_CC = 5 V      Top Trace: Output 5 V/Div.

TIME = 20 µs/Div.   Bottom Trace: Capacitor Voltage 1 V/Div.

R_A = 3.9 kΩ

R_B = 9 kΩ

C = 0.01 µF

Figure 7. Astable Waveforms

The charge time (output high) is given by

And the discharge time (output low) by:

Thus the total period is:

The frequency of oscillation is:

Equation 4.

Figure 8 may be used for quick determination of these RC Values. The duty cycle, as a fraction of total period that the output is low, is:

Equation 5.

Figure 8. Free-Running Frequency