JAJSDF8B March   2017  – July 2019 LMK04616

PRODUCTION DATA.  

  1. 1特長
  2. 2アプリケーション
  3. 3概要
    1.     概略回路図
  4. 4改訂履歴
  5. 5概要 (続き)
    1. 5.1 Device Comparison Table
    2. 5.2 Pin Configuration and Functions
      1.      Pin Functions: LMK04616
    3. 5.3 Specifications
      1. 5.3.1  Absolute Maximum Ratings
      2. 5.3.2  ESD Ratings
      3. 5.3.3  Recommended Operating Conditions
      4. 5.3.4  Thermal Information
      5. 5.3.5  Digital Input and Output Characteristics (CLKin_SEL, STATUSx, SYNC, RESETN)
      6. 5.3.6  Clock Input Characteristics (CLKinX)
      7. 5.3.7  Clock Input Characteristics (OSCin)
      8. 5.3.8  PLL1 Specification Characteristics
      9. 5.3.9  PLL2 Specification Characteristics
      10. 5.3.10 Clock Output Type Characteristics (CLKoutX)
      11. 5.3.11 Oscillator Output Characteristics (OSCout)
      12. 5.3.12 Jitter and Phase Noise Characteristics for CLKoutX and OSCout
      13. 5.3.13 Clock Output Skew and Isolation Characteristics
      14. 5.3.14 Clock Output Delay Characteristics
      15. 5.3.15 DEFAULT POWER on RESET CLOCK OUTPUT Characteristics
      16. 5.3.16 Power Supply Characteristics
      17. 5.3.17 Typical Power Supply Noise Rejection Characteristics
      18. 5.3.18 SPI Interface Timing
      19. 5.3.19 Timing Diagram
      20. 5.3.20 Typical Characteristics
        1. 5.3.20.1 Clock Output AC Characteristics
    4. 5.4 Parameter Measurement Information
      1. 5.4.1 Differential Voltage Measurement Terminology
      2. 5.4.2 Output Termination Scheme
        1. 5.4.2.1 HSDS 4/6/8mA
        2. 5.4.2.2 HCSL
        3. 5.4.2.3 LVCMOS
    5. 5.5 Detailed Description
      1. 5.5.1 Overview
        1. 5.5.1.1 Jitter Cleaning
        2. 5.5.1.2 Four Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*, CLKin2/CLKin2*, and CLKin3/CLKin3*)
        3. 5.5.1.3 VCXO Buffered Output
        4. 5.5.1.4 Frequency Holdover
        5. 5.5.1.5 Integrated Programmable PLL1 and PLL2 Loop Filter
        6. 5.5.1.6 Internal VCOs
        7. 5.5.1.7 Clock Distribution
          1. 5.5.1.7.1 Output Clock Divider
          2. 5.5.1.7.2 Output Clock Delay
          3. 5.5.1.7.3 Glitchless Half-Step and Glitchless Analog Delay
          4. 5.5.1.7.4 Programmable Output Formats
          5. 5.5.1.7.5 Clock Output SYNChronization
        8. 5.5.1.8 Status Pins
      2. 5.5.2 Functional Block Diagram
      3. 5.5.3 Feature Description
        1. 5.5.3.1 Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*, CLKin2/CLKin2*, and CLKin3/CLKin3*)
          1. 5.5.3.1.1 Input Clock Switching
            1. 5.5.3.1.1.1 Input Clock Switching – Register Select Mode
            2. 5.5.3.1.1.2 Input Clock Switching – Pin Select Mode (CLKin_SEL, STATUS0)
              1. 5.5.3.1.1.2.1 Configuring Pin Select Mode
            3. 5.5.3.1.1.3 Input Clock Switching – Automatic Mode
          2. 5.5.3.1.2 Loss of Signal Detection – LOS
            1. 5.5.3.1.2.1 LOS – Assertion
            2. 5.5.3.1.2.2 LOS – Reference Clock Recovery
          3. 5.5.3.1.3 Driving CLKin and OSCin Inputs
            1. 5.5.3.1.3.1 Driving CLKin and OSCin Pins With a Differential Source
            2. 5.5.3.1.3.2 Driving CLKin and OSCin Pins With a Single-Ended Source
        2. 5.5.3.2 Clock Outputs (CLKoutX)
          1. 5.5.3.2.1 HCSL
          2. 5.5.3.2.2 HSDS
          3. 5.5.3.2.3 SYNC
          4. 5.5.3.2.4 Digital Delay
            1. 5.5.3.2.4.1 Fixed Digital Delay
            2. 5.5.3.2.4.2 Dynamic Digital Delay
          5. 5.5.3.2.5 Analog Delay
        3. 5.5.3.3 OSCout
          1. 5.5.3.3.1 Pin-Controlled OSCout Divider
        4. 5.5.3.4 STATUS0/1 and SYNC Pin Functions
          1. 5.5.3.4.1 Common STATUS0/1 and SYNC Pin Functions
          2. 5.5.3.4.2 Additional STATUS0 Pin Functions
          3. 5.5.3.4.3 Additional SYNC Pin Functions
        5. 5.5.3.5 PLL1 and PLL2
          1. 5.5.3.5.1 PLL1
            1. 5.5.3.5.1.1 PLL1 Proportional Modes
            2. 5.5.3.5.1.2 PLL1 Higher Order Poles
          2. 5.5.3.5.2 PLL2
            1. 5.5.3.5.2.1 PLL2 Divider
            2. 5.5.3.5.2.2 PLL2 Input Modes
            3. 5.5.3.5.2.3 PLL2 Loop Filter
            4. 5.5.3.5.2.4 PLL2 3rd Order Loop Filter
            5. 5.5.3.5.2.5 PLL2 Voltage Controlled Oscillator (VCO)
            6. 5.5.3.5.2.6 Examples of PLL2 Setting
          3. 5.5.3.5.3 Digital Lock Detect
            1. 5.5.3.5.3.1 Calculating Digital Lock Detect Frequency Accuracy
        6. 5.5.3.6 Holdover
          1. 5.5.3.6.1 Holdover Flowchart
          2. 5.5.3.6.2 Enable Holdover
            1. 5.5.3.6.2.1 Automatic Tracked CTRL_VCXO Holdover Mode
          3. 5.5.3.6.3 Enter Holdover
            1. 5.5.3.6.3.1 LOS_x Detect
            2. 5.5.3.6.3.2 PLL1 DLD Detect
            3. 5.5.3.6.3.3 CTRL_VCXO Rail Detect
              1. 5.5.3.6.3.3.1 Absolute Limits
              2. 5.5.3.6.3.3.2 Relative Limits
            4. 5.5.3.6.3.4 Manual Holdover Enable – Register Control
            5. 5.5.3.6.3.5 Manual Holdover Enable – Pin Control
            6. 5.5.3.6.3.6 Start-Up into Holdover
          4. 5.5.3.6.4 During Holdover
          5. 5.5.3.6.5 Exiting Holdover
          6. 5.5.3.6.6 Holdover Frequency Accuracy
          7. 5.5.3.6.7 Holdover Mode – Automatic Exit by LOS Deassertion
          8. 5.5.3.6.8 Holdover Mode – Automatic Exit of Holdover With Holdover Counter
        7. 5.5.3.7 JEDEC JESD204B
          1. 5.5.3.7.1 SYNC Pins
          2. 5.5.3.7.2 SYNC modes
          3. 5.5.3.7.3 SYSREF Modes
            1. 5.5.3.7.3.1 SYSREF Pulser
              1. 5.5.3.7.3.1.1 SPI Pulser Mode
              2. 5.5.3.7.3.1.2 Pin Pulser Mode
              3. 5.5.3.7.3.1.3 Multiple SYSREF Frequencies
            2. 5.5.3.7.3.2 Continuous SYSREF
            3. 5.5.3.7.3.3 SYSREF Request
          4. 5.5.3.7.4 How to Enable SYSREF
            1. 5.5.3.7.4.1 Setup Example 1: Pulser Mode, Pin Controlled
            2. 5.5.3.7.4.2 Setup Example 2: Pulser Mode, Spi Controlled
        8. 5.5.3.8 Zero Delay Mode (ZDM)
        9. 5.5.3.9 Power-Up Sequence
      4. 5.5.4 Device Functional Modes
        1. 5.5.4.1 Dual PLL
        2. 5.5.4.2 Single PLL
        3. 5.5.4.3 PLL2 Bypass
        4. 5.5.4.4 Clock Distribution
      5. 5.5.5 Programming
        1. 5.5.5.1 Recommended Programming Sequence
          1. 5.5.5.1.1 Readback
      6. 5.5.6 Register Maps
        1. 5.5.6.1 Register Map for Device Programming
        2. 5.5.6.2 Device Register Descriptions
          1. 5.5.6.2.1   CONFIGA
          2. 5.5.6.2.2   RESERVED1
          3. 5.5.6.2.3   RESERVED2
          4. 5.5.6.2.4   CHIP_TYPE
          5. 5.5.6.2.5   CHIP_ID_BY1
          6. 5.5.6.2.6   CHIP_ID_BY0
          7. 5.5.6.2.7   CHIP_VER
          8. 5.5.6.2.8   RESERVED3
          9. 5.5.6.2.9   RESERVED4
          10. 5.5.6.2.10  RESERVED5
          11. 5.5.6.2.11  RESERVED6
          12. 5.5.6.2.12  RESERVED7
          13. 5.5.6.2.13  VENDOR_ID_BY1
          14. 5.5.6.2.14  VENDOR_ID_BY0
          15. 5.5.6.2.15  RESERVED8
          16. 5.5.6.2.16  RESERVED9
          17. 5.5.6.2.17  STARTUP_CFG
          18. 5.5.6.2.18  STARTUP
          19. 5.5.6.2.19  DIGCLKCTRL
          20. 5.5.6.2.20  PLL2REFCLKDIV
          21. 5.5.6.2.21  GLBL_SYNC_SYSREF
          22. 5.5.6.2.22  CLKIN_CTRL0
          23. 5.5.6.2.23  CLKIN_CTRL1
          24. 5.5.6.2.24  CLKIN0CTRL
          25. 5.5.6.2.25  CLKIN1CTRL
          26. 5.5.6.2.26  CLKIN2CTRL
          27. 5.5.6.2.27  CLKIN3CTRL
          28. 5.5.6.2.28  CLKIN0RDIV_BY1
          29. 5.5.6.2.29  CLKIN0RDIV_BY0
          30. 5.5.6.2.30  CLKIN1RDIV_BY1
          31. 5.5.6.2.31  CLKIN1RDIV_BY0
          32. 5.5.6.2.32  CLKIN2RDIV_BY1
          33. 5.5.6.2.33  CLKIN2RDIV_BY0
          34. 5.5.6.2.34  CLKIN3RDIV_BY1
          35. 5.5.6.2.35  CLKIN3RDIV_BY0
          36. 5.5.6.2.36  CLKIN0LOS_REC_CNT
          37. 5.5.6.2.37  CLKIN0LOS_LAT_SEL
          38. 5.5.6.2.38  CLKIN1LOS_REC_CNT
          39. 5.5.6.2.39  CLKIN1LOS_LAT_SEL
          40. 5.5.6.2.40  CLKIN2LOS_REC_CNT
          41. 5.5.6.2.41  CLKIN2LOS_LAT_SEL
          42. 5.5.6.2.42  CLKIN3LOS_REC_CNT
          43. 5.5.6.2.43  CLKIN3LOS_LAT_SEL
          44. 5.5.6.2.44  CLKIN_SWCTRL0
          45. 5.5.6.2.45  CLKIN_SWCTRL1
          46. 5.5.6.2.46  CLKIN_SWCTRL2
          47. 5.5.6.2.47  OSCIN_CTRL
          48. 5.5.6.2.48  OSCOUT_CTRL
          49. 5.5.6.2.49  OSCOUT_DIV
          50. 5.5.6.2.50  OSCOUT_DRV
          51. 5.5.6.2.51  OUTCH_SWRST
          52. 5.5.6.2.52  OUTCH01CNTL0
          53. 5.5.6.2.53  OUTCH01CNTL1
          54. 5.5.6.2.54  OUTCH23CNTL0
          55. 5.5.6.2.55  OUTCH23CNTL1
          56. 5.5.6.2.56  OUTCH45CNTL0
          57. 5.5.6.2.57  OUTCH45CNTL1
          58. 5.5.6.2.58  OUTCH67CNTL0
          59. 5.5.6.2.59  OUTCH67CNTL1
          60. 5.5.6.2.60  OUTCH89CNTL0
          61. 5.5.6.2.61  OUTCH89CNTL1
          62. 5.5.6.2.62  OUTCH1011CNTL0
          63. 5.5.6.2.63  OUTCH1011CNTL1
          64. 5.5.6.2.64  OUTCH1213CNTL0
          65. 5.5.6.2.65  OUTCH1213CNTL1
          66. 5.5.6.2.66  OUTCH1415CNTL0
          67. 5.5.6.2.67  OUTCH1415CNTL1
          68. 5.5.6.2.68  OUTCH01DIV_BY1
          69. 5.5.6.2.69  OUTCH01DIV_BY0
          70. 5.5.6.2.70  OUTCH23DIV_BY1
          71. 5.5.6.2.71  OUTCH23DIV_BY0
          72. 5.5.6.2.72  OUTCH45DIV_BY1
          73. 5.5.6.2.73  OUTCH45DIV_BY0
          74. 5.5.6.2.74  OUTCH67DIV_BY1
          75. 5.5.6.2.75  OUTCH67DIV_BY0
          76. 5.5.6.2.76  OUTCH89DIV_BY1
          77. 5.5.6.2.77  OUTCH89DIV_BY0
          78. 5.5.6.2.78  OUTCH1011DIV_BY1
          79. 5.5.6.2.79  OUTCH1011DIV_BY0
          80. 5.5.6.2.80  OUTCH1213DIV_BY1
          81. 5.5.6.2.81  OUTCH1213DIV_BY0
          82. 5.5.6.2.82  OUTCH1415DIV_BY1
          83. 5.5.6.2.83  OUTCH1415DIV_BY0
          84. 5.5.6.2.84  OUTCH_DIV_INV
          85. 5.5.6.2.85  PLL1CTRL0
          86. 5.5.6.2.86  PLL1CTRL1
          87. 5.5.6.2.87  PLL1CTRL2
          88. 5.5.6.2.88  PLL1_SWRST
          89. 5.5.6.2.89  PLL1WNDWSIZE
          90. 5.5.6.2.90  PLL1STRCELL
          91. 5.5.6.2.91  PLL1CPSETTING
          92. 5.5.6.2.92  PLL1CPSETTING_FL
          93. 5.5.6.2.93  PLL1_HOLDOVER_CTRL1
          94. 5.5.6.2.94  PLL1_HOLDOVER_MAXCNT_BY3
          95. 5.5.6.2.95  PLL1_HOLDOVER_MAXCNT_BY2
          96. 5.5.6.2.96  PLL1_HOLDOVER_MAXCNT_BY1
          97. 5.5.6.2.97  PLL1_HOLDOVER_MAXCNT_BY0
          98. 5.5.6.2.98  PLL1_NDIV_BY1
          99. 5.5.6.2.99  PLL1_NDIV_BY0
          100. 5.5.6.2.100 PLL1_LOCKDET_CYC_CNT_BY2
          101. 5.5.6.2.101 PLL1_LOCKDET_CYC_CNT_BY1
          102. 5.5.6.2.102 PLL1_LOCKDET_CYC_CNT_BY0
          103. 5.5.6.2.103 RSRVD_0x66
          104. 5.5.6.2.104 RSRVD_0x67
          105. 5.5.6.2.105 RSRVD_0x68
          106. 5.5.6.2.106 RSRVD_0x69
          107. 5.5.6.2.107 PLL1_STRG
          108. 5.5.6.2.108 PLL1RCCLKDIV
          109. 5.5.6.2.109 PLL2_CTRL0
          110. 5.5.6.2.110 PLL2_CTRL1
          111. 5.5.6.2.111 PLL2_CTRL2
          112. 5.5.6.2.112 PLL2_SWRST
          113. 5.5.6.2.113 PLL2_LF_C4R4
          114. 5.5.6.2.114 PLL2_LF_C3R3
          115. 5.5.6.2.115 PLL2_CP_SETTING
          116. 5.5.6.2.116 PLL2_NDIV_BY1
          117. 5.5.6.2.117 PLL2_NDIV_BY0
          118. 5.5.6.2.118 PLL2_RDIV_BY1
          119. 5.5.6.2.119 PLL2_RDIV_BY0
          120. 5.5.6.2.120 PLL2_STRG_INIT_BY1
          121. 5.5.6.2.121 PLL2_STRG_INIT_BY0
          122. 5.5.6.2.122 RAILDET_UP
          123. 5.5.6.2.123 RAILDET_LOW
          124. 5.5.6.2.124 PLL2_AC_CTRL
          125. 5.5.6.2.125 PLL2_CURR_STOR_CELL
          126. 5.5.6.2.126 PLL2_AC_THRESHOLD
          127. 5.5.6.2.127 PLL2_AC_STRT_THRESHOLD
          128. 5.5.6.2.128 PLL2_AC_WAIT_CTRL
          129. 5.5.6.2.129 PLL2_AC_JUMPSTEP
          130. 5.5.6.2.130 PLL2_LD_WNDW_SIZE
          131. 5.5.6.2.131 PLL2_LD_WNDW_SIZE_INITIAL
          132. 5.5.6.2.132 PLL2_LOCKDET_CYC_CNT_BY2
          133. 5.5.6.2.133 PLL2_LOCKDET_CYC_CNT_BY1
          134. 5.5.6.2.134 PLL2_LOCKDET_CYC_CNT_BY0
          135. 5.5.6.2.135 PLL2_LOCKDET_CYC_CNT_INITIAL_BY2
          136. 5.5.6.2.136 PLL2_LOCKDET_CYC_CNT_INITIAL_BY1
          137. 5.5.6.2.137 PLL2_LOCKDET_CYC_CNT_INITIAL_BY0
          138. 5.5.6.2.138 IOCTRL_SPI0
          139. 5.5.6.2.139 IOCTRL_SPI1
          140. 5.5.6.2.140 IOTEST_SDIO
          141. 5.5.6.2.141 IOTEST_SCL
          142. 5.5.6.2.142 IOTEST_SCS
          143. 5.5.6.2.143 IOCTRL_STAT0
          144. 5.5.6.2.144 IOCTRL_STAT1
          145. 5.5.6.2.145 STAT1MUX
          146. 5.5.6.2.146 STAT0MUX
          147. 5.5.6.2.147 STATPLL2CLKDIV
          148. 5.5.6.2.148 IOTEST_STAT0
          149. 5.5.6.2.149 IOTEST_STAT1
          150. 5.5.6.2.150 IOCTRL_SYNC
          151. 5.5.6.2.151 DUMMY_REGISTER_1
          152. 5.5.6.2.152 IOCTRL_CLKINSEL1
          153. 5.5.6.2.153 IOTEST_CLKINSEL1
          154. 5.5.6.2.154 PLL1_TSTMODE
          155. 5.5.6.2.155 PLL2_CTRL
          156. 5.5.6.2.156 PLL2_RDIV_CLKEN
          157. 5.5.6.2.157 PLL2_NDIV_CLKEN
          158. 5.5.6.2.158 STATUS
          159. 5.5.6.2.159 PLL2_DLD_EN
          160. 5.5.6.2.160 PLL2_DUAL_LOOP
          161. 5.5.6.2.161 CH01_DDLY_BY0
          162. 5.5.6.2.162 CH23_DDLY_BY0
          163. 5.5.6.2.163 CH45_DDLY_BY0
          164. 5.5.6.2.164 CH67_DDLY_BY0
          165. 5.5.6.2.165 CH89_DDLY_BY0
          166. 5.5.6.2.166 CH1011_DDLY_BY0
          167. 5.5.6.2.167 CH1213_DDLY_BY0
          168. 5.5.6.2.168 CH1415_DDLY_BY0
          169. 5.5.6.2.169 OUTCH0_JESD_CTRL
          170. 5.5.6.2.170 OUTCH1_JESD_CTRL
          171. 5.5.6.2.171 OUTCH2_JESD_CTRL
          172. 5.5.6.2.172 OUTCH3_JESD_CTRL
          173. 5.5.6.2.173 OUTCH4_JESD_CTRL
          174. 5.5.6.2.174 OUTCH5_JESD_CTRL
          175. 5.5.6.2.175 OUTCH6_JESD_CTRL
          176. 5.5.6.2.176 OUTCH7_JESD_CTRL
          177. 5.5.6.2.177 OUTCH8_JESD_CTRL
          178. 5.5.6.2.178 OUTCH9_JESD_CTRL
          179. 5.5.6.2.179 OUTCH10_JESD_CTRL
          180. 5.5.6.2.180 OUTCH11_JESD_CTRL
          181. 5.5.6.2.181 OUTCH12_JESD_CTRL
          182. 5.5.6.2.182 OUTCH13_JESD_CTRL
          183. 5.5.6.2.183 OUTCH14_JESD_CTRL
          184. 5.5.6.2.184 OUTCH15_JESD_CTRL
          185. 5.5.6.2.185 CLKMUXVECTOR
          186. 5.5.6.2.186 OUTCH01CNTL2
          187. 5.5.6.2.187 OUTCH23CNTL2
          188. 5.5.6.2.188 OUTCH45CNTL2
          189. 5.5.6.2.189 OUTCH67CNTL2
          190. 5.5.6.2.190 OUTCH89CNTL2
          191. 5.5.6.2.191 OUTCH1011CNTL2
          192. 5.5.6.2.192 OUTCH1213CNTL2
          193. 5.5.6.2.193 OUTCH1415CNTL2
          194. 5.5.6.2.194 OUTCH0_JESD_CTRL1
          195. 5.5.6.2.195 OUTCH1_JESD_CTRL1
          196. 5.5.6.2.196 OUTCH2_JESD_CTRL1
          197. 5.5.6.2.197 OUTCH3_JESD_CTRL1
          198. 5.5.6.2.198 OUTCH4_JESD_CTRL1
          199. 5.5.6.2.199 OUTCH5_JESD_CTRL1
          200. 5.5.6.2.200 OUTCH6_JESD_CTRL1
          201. 5.5.6.2.201 OUTCH7_JESD_CTRL1
          202. 5.5.6.2.202 OUTCH8_JESD_CTRL1
          203. 5.5.6.2.203 OUTCH9_JESD_CTRL1
          204. 5.5.6.2.204 OUTCH10_JESD_CTRL1
          205. 5.5.6.2.205 OUTCH11_JESD_CTRL1
          206. 5.5.6.2.206 OUTCH12_JESD_CTRL1
          207. 5.5.6.2.207 OUTCH13_JESD_CTRL1
          208. 5.5.6.2.208 OUTCH14_JESD_CTRL1
          209. 5.5.6.2.209 OUTCH15_JESD_CTRL1
          210. 5.5.6.2.210 SYSREF_PLS_CNT
          211. 5.5.6.2.211 SYNCMUX
          212. 5.5.6.2.212 IOTEST_SYNC
          213. 5.5.6.2.213 OUTCH_ZDM
          214. 5.5.6.2.214 PLL2_CTRL3
          215. 5.5.6.2.215 PLL1_HOLDOVER_CTRL0
          216. 5.5.6.2.216 IOCTRL_SYNC_1
          217. 5.5.6.2.217 OUTCH_TOP_JESD_CTRL
          218. 5.5.6.2.218 OUTCH_BOT_JESD_CTRL
          219. 5.5.6.2.219 OUTCH_JESD_CTRL1
          220. 5.5.6.2.220 PLL2_CTRL4
          221. 5.5.6.2.221 PLL2_CTRL5
          222. 5.5.6.2.222 PLL2_CTRL6
          223. 5.5.6.2.223 PLL2_CTRL7
    6. 5.6 Application and Implementation
      1. 5.6.1 Application Information
        1. 5.6.1.1 Digital Lock Detect Frequency Accuracy
          1. 5.6.1.1.1 Minimum Lock Time Calculation Example
      2. 5.6.2 Typical Application
        1. 5.6.2.1 Design Requirements
        2. 5.6.2.2 Detailed Design Procedure
          1. 5.6.2.2.1 PLL Loop Filter Design
          2. 5.6.2.2.2 Clock Output Assignment
          3. 5.6.2.2.3 Calculation Using LCM
          4. 5.6.2.2.4 Device Programming
          5. 5.6.2.2.5 Device Selection
          6. 5.6.2.2.6 Clock Architect
        3. 5.6.2.3 Application Curves
      3. 5.6.3 Do's and Don'ts
        1. 5.6.3.1 Pin Connection Recommendations
    7. 5.7 Power Supply Recommendations
      1. 5.7.1 Recommended Power Supply Connection
      2. 5.7.2 Current Consumption / Power Dissipation Calculations
    8. 5.8 Layout
      1. 5.8.1 Layout Guidelines
        1. 5.8.1.1 CLKin and OSCin
        2. 5.8.1.2 CLKout
      2. 5.8.2 Layout Example
  6. 6デバイスおよびドキュメントのサポート
    1. 6.1 デバイス・サポート
      1. 6.1.1 開発サポート
        1. 6.1.1.1 クロック設計ツール
        2. 6.1.1.2 Clock Architect
        3. 6.1.1.3 TICS Pro
    2. 6.2 ドキュメントの更新通知を受け取る方法
    3. 6.3 コミュニティ・リソース
    4. 6.4 商標
    5. 6.5 静電気放電に関する注意事項
    6. 6.6 Glossary
  7. 7メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5.6.1 Register Map for Device Programming

Table 24 provides the register map for device programming. Any register can be read from the same data address it is written to.

Table 24. Register Map

ADDRESS DATA
[15:0] D7 D6 D5 D4 D3 D2 D1 D0
0x00 SWRST LSB_FIRST ADDR_ASCEND SDO_ACTIVE SDO_ACTIVE_CPY ADDR_ASCEND_CPY LSB_FIRST_CPY SWRST_CPY
0x01 RSRVD RSRVD1
0x02 RSRVD RSRVD2[1:0]
0x03 DEVID[1:0] RSRVD CHIPTYPE[3:0]
0x04 CHIPID[15:8]
0x05 CHIPID[7:0]
0x06 CHIPVER[7:0]
0x07 RSRVD RSRVD3
0x08 RSRVD RSRVD4
0x09 RSRVD RSRVD5
0x0A RSRVD RSRVD6
0x0B RSRVD RSRVD7
0x0C VENDORID[15:8]
0x0D VENDORID[7:0]
0x0E RSRVD RSRVD8
0x0F RSRVD RSRVD9
0x10 RSRVD OUTCH_MUTE CLKINBLK_LOSLDO_EN CH8TO15EN CH0TO7EN PLL2EN PLL1EN
0x11 RSRVD DEV_STARTUP
0x12 RSRVD DIG_CLK_EN PLL2_DIG_CLK_EN PORCLKAFTERLOCK
0x13 RSRVD PLL2_REF_DIGCLK_DIV[4:0]
0x14 EN_SYNC_PIN_FUNC RSRVD GLOBAL_CONT_SYSREF GLOBAL_SYSREF INV_SYNC_INPUT_SYNC_CLK SYNC_PIN_FUNC[1:0] GLOBAL_SYNC
0x15 RSRVD CLKIN_STAGGER_EN CLKIN_SWRST RSRVD CLKINSEL1_INV
0x16 CLKINBLK_ALL_EN CLKINSEL1_MODE[1:0] CLKINBLK_EN_BUF_CLK_PLL CLKINBLK_EN_BUF_BYP_PLL RSRVD RSRVD RSRVD
0x17 RSRVD CLKIN0_PLL1_INV CLKIN0_LOS_FRQ_DBL_EN CLKIN0_EN CLKIN0_SE_MODE CLKIN0_PRIO[2:0]
0x18 RSRVD CLKIN1_PLL1_INV CLKIN1_LOS_FRQ_DBL_EN CLKIN1_EN CLKIN1_SE_MODE CLKIN1_PRIO[2:0]
0x19 RSRVD CLKIN2_PLL1_INV CLKIN2_LOS_FRQ_DBL_EN CLKIN2_EN CLKIN2_SE_MODE CLKIN2_PRIO[2:0]
0x1A RSRVD CLKIN3_PLL1_INV CLKIN3_LOS_FRQ_DBL_EN CLKIN3_EN CLKIN3_SE_MODE CLKIN3_PRIO[2:0]
0x1B CLKIN0_PLL1_RDIV[15:8]
0x1C CLKIN0_PLL1_RDIV[7:0]
0x1D CLKIN1_PLL1_RDIV[15:8]
0x1E CLKIN1_PLL1_RDIV[7:0]
0x1F CLKIN2_PLL1_RDIV[15:8]
0x20 CLKIN2_PLL1_RDIV[7:0]
0x21 CLKIN3_PLL1_RDIV[15:8]
0x22 CLKIN3_PLL1_RDIV[7:0]
0x23 CLKIN0_LOS_REC_CNT[7:0]
0x24 CLKIN0_LOS_LAT_SEL[7:0]
0x25 CLKIN1_LOS_REC_CNT[7:0]
0x26 CLKIN1_LOS_LAT_SEL[7:0]
0x27 CLKIN2_LOS_REC_CNT[7:0]
0x28 CLKIN2_LOS_LAT_SEL[7:0]
0x29 CLKIN3_LOS_REC_CNT[7:0]
0x2A CLKIN3_LOS_LAT_SEL[7:0]
0x2B RSRVD SW_CLKLOS_TMR[4:0]
0x2C SW_REFINSEL[3:0] SW_LOS_CH_SEL[3:0]
0x2D RSRVD SW_ALLREFSON_TMR[4:0]
0x2E RSRVD OSCIN_PD_LDO OSCIN_SE_MODE OSCIN_BUF_TO_OSCOUT_EN OSCIN_OSCINSTAGE_EN OSCIN_BUF_REF_EN OSCIN_BUF_LOS_EN
0x2F OSCOUT_LVCMOS_WEAK_DRIVE OSCOUT_DIV_REGCONTROL OSCOUT_PINSEL_DIV[1:0] OSCOUT_SEL_VBG OSCOUT_DIV_CLKEN OSCOUT_SWRST OSCOUT_SEL_SRC
0x30 OSCOUT_DIV[7:0]
0x31 OSCOUT_DRV_MUTE[1:0] OSCOUT_DRV_MODE[5:0]
0x32 CH1415_SWRST CH1213_SWRST CH1011_SWRST CH89_SWRST CH67_SWRST CH45_SWRST CH23_SWRST CH01_SWRST
0x33 OUTCH01_LDO_BYP_MODE OUTCH01_LDO_MASK OUTCH0_DRIV_MODE[5:0]
0x34 OUTCH1_DRIV_MODE[5:0] DIV_DCC_EN_CH0_1 OUTCH01_DIV_CLKEN
0x35 OUTCH23_LDO_BYP_MODE OUTCH23_LDO_MASK OUTCH2_DRIV_MODE[5:0]
0x36 OUTCH3_DRIV_MODE[5:0] DIV_DCC_EN_CH2_3 OUTCH23_DIV_CLKEN
0x37 OUTCH45_LDO_BYP_MODE OUTCH45_LDO_MASK OUTCH4_DRIV_MODE[5:0]
0x38 OUTCH5_DRIV_MODE[5:0] DIV_DCC_EN_CH4_5 OUTCH45_DIV_CLKEN
0x39 OUTCH67_LDO_BYP_MODE OUTCH67_LDO_MASK OUTCH6_DRIV_MODE[5:0]
0x3A OUTCH7_DRIV_MODE[5:0] DIV_DCC_EN_CH6_7 OUTCH67_DIV_CLKEN
0x3B OUTCH89_LDO_BYP_MODE OUTCH89_LDO_MASK OUTCH8_DRIV_MODE[5:0]
0x3C OUTCH9_DRIV_MODE[5:0] DIV_DCC_EN_CH8_9 OUTCH89_DIV_CLKEN
0x3D OUTCH1011_LDO_BYP_MODE OUTCH1011_LDO_MASK OUTCH10_DRIV_MODE[5:0]
0x3E OUTCH11_DRIV_MODE[5:0] DIV_DCC_EN_CH10_11 OUTCH1011_DIV_CLKEN
0x3F OUTCH1213_LDO_BYP_MODE OUTCH1213_LDO_MASK OUTCH12_DRIV_MODE[5:0]
0x40 OUTCH13_DRIV_MODE[5:0] DIV_DCC_EN_CH12_13 OUTCH1213_DIV_CLKEN
0x41 OUTCH1415_LDO_BYP_MODE OUTCH1415_LDO_MASK OUTCH14_DRIV_MODE[5:0]
0x42 OUTCH15_DRIV_MODE[5:0] DIV_DCC_EN_CH14_15 OUTCH1415_DIV_CLKEN
0x43 OUTCH01_DIV[15:8]
0x44 OUTCH01_DIV[7:0]
0x45 OUTCH23_DIV[15:8]
0x46 OUTCH23_DIV[7:0]
0x47 OUTCH45_DIV[15:8]
0x48 OUTCH45_DIV[7:0]
0x49 OUTCH67_DIV[15:8]
0x4A OUTCH67_DIV[7:0]
0x4B OUTCH89_DIV[15:8]
0x4C OUTCH89_DIV[7:0]
0x4D OUTCH1011_DIV[15:8]
0x4E OUTCH1011_DIV[7:0]
0x4F OUTCH1213_DIV[15:8]
0x50 OUTCH1213_DIV[7:0]
0x51 OUTCH1415_DIV[15:8]
0x52 OUTCH1415_DIV[7:0]
0x53 OUTCH1415_DIV_INV OUTCH1213_DIV_INV OUTCH1011_DIV_INV OUTCH89_DIV_INV OUTCH67_DIV_INV OUTCH45_DIV_INV OUTCH23_DIV_INV OUTCH01_DIV_INV
0x54 PLL1_F_30 PLL1_EN_REGULATION PLL1_PD_LD PLL1_DIR_POS_GAIN PLL1_LDO_WAIT_TMR[3:0]
0x55 PLL1_LCKDET_BY_32 PLL1_FAST_LOCK PLL1_LCKDET_LOS_MASK PLL1_FBCLK_INV RSRVD PLL1_BYP_LOS PLL1_PFD_UP_HOLDOVER PLL1_PFD_DOWN_HOLDOVER
0x56 RSRVD PLL1_LOL_NORESET PLL1_RDIV_CLKEN PLL1_RDIV_4CY PLL1_NDIV_CLKEN PLL1_NDIV_4CY
0x57 RSRVD PLL1_HOLDOVER_DLD_SWRST PLL1_RDIV_SWRST PLL1_NDIV_SWRST PLL1_HOLDOVERCNT_SWRST PLL1_HOLDOVER_LOCKDET_SWRST PLL1_SWRST
0x58 PLL1_LD_WNDW_SIZE[7:0]
0x59 PLL1_INTG_FL [3:0] PLL1_INTG [3:0]
0x5A RSRVD PLL1_PROP[6:0]
0x5B RSRVD PLL1_PROP_FL[6:0]
0x5C PLL1_HOLDOVER_EN PLL1_STARTUP_HOLDOVER_EN PLL1_HOLDOVER_FORCE PLL1_HOLDOVER_RAIL_MODE PLL1_HOLDOVER_MAX_CNT_EN PLL1_HOLDOVER_LOS_MASK PLL1_HOLDOVER_LCKDET_MASK PLL1_HOLDOVER_RAILDET_EN
0x5D PLL1_HOLDOVER_MAX_CNT[31:24]
0x5E PLL1_HOLDOVER_MAX_CNT[23:16]
0x5F PLL1_HOLDOVER_MAX_CNT[15:8]
0x60 PLL1_HOLDOVER_MAX_CNT[7:0]
0x61 PLL1_NDIV[15:8]
0x62 PLL1_NDIV[7:0]
0x63 PLL1_LOCKDET_CYC_CNT[23:16]
0x64 PLL1_LOCKDET_CYC_CNT[15:8]
0x65 PLL1_LOCKDET_CYC_CNT[7:0]
0x66 RSRVD
0x67 RSRVD
0x68 RSRVD
0x69 RSRVD
0x6A RSRVD PLL1_STORAGE_CELL[5:0]
0x6B RSRVD PLL1_RC_CLK_EN RSRVD PLL1_RC_CLK_DIV[2:0]
0x6C RSRVD PLL2_VCO_PRESC_LOW_POWER PLL2_BYP_OSC PLL2_BYP_TOP PLL2_BYP_BOT PLL2_GLOBAL_BYP
0x6D PLL2_EN_PULSE_GEN PLL2_RDIV_BYP PLL2_DBL_EN_INV PLL2_PD_VARBIAS PLL2_SMART_TRIM PLL2_LCKDET_LOS_MASK PLL2_RDIV_DBL_EN PLL2_PD_LD
0x6E PLL2_BYP_SYNC_TOP PLL2_BYP_SYNC_BOTTOM PLL2_EN_BYP_BUF PLL2_EN_BUF_SYNC_TOP PLL2_EN_BUF_SYNC_BOTTOM PLL2_EN_BUF_OSCOUT PLL2_EN_BUF_CLK_TOP PLL2_EN_BUF_CLK_BOTTOM
0x6F RSRVD PLL2_RDIV_SWRST PLL2_NDIV_SWRST PLL2_SWRST
0x70 PLL2_C4_LF_SEL[3:0] PLL2_R4_LF_SEL[3:0]
0x71 PLL2_C3_LF_SEL[3:0] PLL2_R3_LF_SEL[3:0]
0x72 RSRVD PLL2_PROP[5:0]
0x73 PLL2_NDIV[15:8]
0x74 PLL2_NDIV[7:0]
0x75 PLL2_RDIV[15:8]
0x76 PLL2_RDIV[7:0]
0x77 PLL2_STRG_INITVAL[15:8]
0x78 PLL2_STRG_INITVAL[7:0]
0x7D RSRVD RAILDET_UPP[5:0]
0x7E RSRVD RAILDET_LOW[5:0]
0x7F RSRVD PLL2_AC_CAL_EN PLL2_PD_AC PLL2_IDACSET_RECAL[1:0] PLL2_AC_REQ PLL2_FAST_ACAL
0x80 RSRVD PLL2_INTG[4:0]
0x81 RSRVD PLL2_AC_THRESHOLD[4:0]
0x82 RSRVD PLL2_AC_STRT_THRESHOLD[4:0]
0x83 PLL2_AC_CMP_WAIT[3:0] PLL2_AC_INIT_WAIT[3:0]
0x84 RSRVD PLL2_AC_JUMP_STEP[3:0]
0x85 PLL2_LD_WNDW_SIZE[7:0]
0x86 PLL2_LD_WNDW_SIZE_INITIAL[7:0]
0x87 PLL2_LOCKDET_CYC_CNT[23:16]
0x88 PLL2_LOCKDET_CYC_CNT[15:8]
0x89 PLL2_LOCKDET_CYC_CNT[7:0]
0x8A PLL2_LOCKDET_CYC_CNT_INITIAL[23:16]
0x8B PLL2_LOCKDET_CYC_CNT_INITIAL[15:8]
0x8C PLL2_LOCKDET_CYC_CNT_INITIAL[7:0]
0x8D SPI_EN_THREE_WIRE_IF RSRVD SPI_SDIO_OUTPUT_MUTE SPI_SDIO_OUTPUT_INV SPI_SDIO_OUTPUT_WEAK_DRIVE SPI_SDIO_EN_PULLUP SPI_SDIO_EN_PULLDOWN
0x8E RSRVD SPI_SCL_EN_PULLUP SPI_SCL_EN_PULLDOWN SPI_SCS_EN_PULLUP SPI_SCS_EN_PULLDOWN
0x8F RSRVD SPI_SDIO_OUTPUT_HIZ SPI_SDIO_ENB_INSTAGE SPI_SDIO_EN_ML_INSTAGE RSRVD SPI_SDIO_OUTPUT_DATA SPI_SDIO_INPUT_Y12 SPI_SDIO_INPUT_M12
0x90 RSRVD SPI_SCL_ENB_INSTAGE SPI_SCL_EN_ML_INSTAGE RSRVD SPI_SCL_INPUT_Y12 SPI_SCL_INPUT_M12
0x91 RSRVD SPI_SCS_ENB_INSTAGE SPI_SCS_EN_ML_INSTAGE RSRVD SPI_SCS_INPUT_Y12 SPI_SCS_INPUT_M12
0x92 STATUS0_MUX_SEL[2:0] STATUS0_OUTPUT_MUTE STATUS0_OUTPUT_INV STATUS0_OUTPUT_WEAK_DRIVE STATUS0_EN_PULLUP STATUS0_EN_PULLDOWN
0x93 STATUS1_MUX_SEL[2:0] STATUS1_OUTPUT_MUTE STATUS1_OUTPUT_INV STATUS1_OUTPUT_WEAK_DRIVE STATUS1_EN_PULLUP STATUS1_EN_PULLDOWN
0x94 STATUS1_INT_MUX[7:0]
0x95 STATUS0_INT_MUX[7:0]
0x96 RSRVD PLL2_REF_CLK_EN RSRVD PLL2_REF_STATCLK_DIV[2:0]
0x97 RSRVD STATUS0_OUTPUT_HIZ STATUS0_ENB_INSTAGE STATUS0_EN_ML_INSTAGE RSRVD STATUS0_OUTPUT_DATA STATUS0_INPUT_Y12 STATUS0_INPUT_M12
0x98 RSRVD STATUS1_OUTPUT_HIZ STATUS1_ENB_INSTAGE STATUS1_EN_ML_INSTAGE RSRVD STATUS1_OUTPUT_DATA STATUS1_INPUT_Y12 STATUS1_INPUT_M12
0x99 SYNC_MUX_SEL[2:0] SYNC_OUTPUT_MUTE SYNC_OUTPUT_INV SYNC_OUTPUT_WEAK_DRIVE SYNC_EN_PULLUP SYNC_EN_PULLDOWN
0x9A RSRVD RSRVD
0x9B RSRVD CLKINSEL1_EN_PULLUP CLKINSEL1_EN_PULLDOWN
0x9C RSRVD CLKINSEL1_ENB_INSTAGE CLKINSEL1_EN_ML_INSTAGE RSRVD CLKINSEL1_INPUT_Y12 CLKINSEL1_INPUT_M12
0xAC PLL1_TSTMODE_REF_FB_EN RSRVD
0xAD RSRVD RESET_PLL2_DLD[1:0] RSRVD PLL2_TSTMODE_REF_FB_EN PD_VCO_LDO[1:0]
0xAF RSRVD RSRVD RSRVD PLL2_RDIV_CLKEN
0xB0 RSRVD RSRVD RSRVD PLL2_NDIV_CLKEN
0xBE RSRVD LOS HOLDOVER_DLD HOLDOVER_LOL HOLDOVER_LOS PLL2_LCK_DET PLL1_LCK_DET
0xF6 RSRVD PLL2_DLD_EN RSRVD
0xFD OUTCH01_DDLY[7:0]
0xFF OUTCH23_DDLY[7:0]
0x101 OUTCH45_DDLY[7:0]
0x103 OUTCH67_DDLY[7:0]
0x105 OUTCH89_DDLY[7:0]
0x107 OUTCH1011_DDLY[7:0]
0x109 OUTCH1213_DDLY[7:0]
0x10B OUTCH1415_DDLY[7:0]
0x10C RSRVD CH0_ADLY[4:0] CH0_ADLY_EN RSRVD
0x10D RSRVD CH1_ADLY[4:0] CH1_ADLY_EN RSRVD
0x10E RSRVD CH2_ADLY[4:0] CH2_ADLY_EN RSRVD
0x10F RSRVD CH3_ADLY[4:0] CH3_ADLY_EN RSRVD
0x110 RSRVD CH4_ADLY[4:0] CH4_ADLY_EN RSRVD
0x111 RSRVD CH5_ADLY[4:0] CH5_ADLY_EN RSRVD
0x112 RSRVD CH6_ADLY[4:0] CH6_ADLY_EN RSRVD
0x113 RSRVD CH7_ADLY[4:0] CH7_ADLY_EN RSRVD
0x114 RSRVD CH8_ADLY[4:0] CH8_ADLY_EN RSRVD
0x115 RSRVD CH9_ADLY[4:0] CH9_ADLY_EN RSRVD
0x116 RSRVD CH10_ADLY[4:0] CH10_ADLY_EN RSRVD
0x117 RSRVD CH11_ADLY[4:0] CH11_ADLY_EN RSRVD
0x118 RSRVD CH12_ADLY[4:0] CH12_ADLY_EN RSRVD
0x119 RSRVD CH13_ADLY[4:0] CH13_ADLY_EN RSRVD
0x11A RSRVD CH14_ADLY[4:0] CH14_ADLY_EN RSRVD
0x11B RSRVD CH15_ADLY[4:0] CH15_ADLY_EN RSRVD
0x124 RSRVD CLKMUX[3:0]
0x127 SYSREF_BYP_DYNDIGDLY_GATING_CH0_1 SYSREF_BYP_ANALOGDLY_GATING_CH0_1 SYNC_EN_CH0_1 HS_EN_CH0_1 DRIV_1_SLEW[1:0] DRIV_0_SLEW[1:0]
0x128 SYSREF_BYP_DYNDIGDLY_GATING_CH2_3 SYSREF_BYP_ANALOGDLY_GATING_CH2_3 SYNC_EN_CH2_3 HS_EN_CH2_3 DRIV_3_SLEW[1:0] DRIV_2_SLEW[1:0]
0x129 SYSREF_BYP_DYNDIGDLY_GATING_CH4_5 SYSREF_BYP_ANALOGDLY_GATING_CH4_5 SYNC_EN_CH4_5 HS_EN_CH4_5 DRIV_5_SLEW[1:0] DRIV_4_SLEW[1:0]
0x12A SYSREF_BYP_DYNDIGDLY_GATING_CH6_7 SYSREF_BYP_ANALOGDLY_GATING_CH6_7 SYNC_EN_CH6_7 HS_EN_CH6_7 DRIV_7_SLEW[1:0] DRIV_6_SLEW[1:0]
0x12B SYSREF_BYP_DYNDIGDLY_GATING_CH8_9 SYSREF_BYP_ANALOGDLY_GATING_CH8_9 SYNC_EN_CH8_9 HS_EN_CH8_9 DRIV_9_SLEW[1:0] DRIV_8_SLEW[1:0]
0x12C SYSREF_BYP_DYNDIGDLY_GATING_CH10_11 SYSREF_BYP_ANALOGDLY_GATING_CH10_11 SYNC_EN_CH10_11 HS_EN_CH10_11 DRIV_11_SLEW[1:0] DRIV_10_SLEW[1:0]
0x12D SYSREF_BYP_DYNDIGDLY_GATING_CH12_13 SYSREF_BYP_ANALOGDLY_GATING_CH12_13 SYNC_EN_CH12_13 HS_EN_CH12_13 DRIV_13_SLEW[1:0] DRIV_12_SLEW[1:0]
0x12E SYSREF_BYP_DYNDIGDLY_GATING_CH14_15 SYSREF_BYP_ANALOGDLY_GATING_CH14_15 SYNC_EN_CH14_15 HS_EN_CH14_15 DRIV_15_SLEW[1:0] DRIV_14_SLEW[1:0]
0x12F RSRVD DYN_DDLY_CH0[2:0]
0x130 RSRVD DYN_DDLY_CH1[2:0]
0x131 RSRVD DYN_DDLY_CH2[2:0]
0x132 RSRVD DYN_DDLY_CH3[2:0]
0x133 RSRVD DYN_DDLY_CH4[2:0]
0x134 RSRVD DYN_DDLY_CH5[2:0]
0x135 RSRVD DYN_DDLY_CH6[2:0]
0x136 RSRVD DYN_DDLY_CH7[2:0]
0x137 RSRVD DYN_DDLY_CH8[2:0]
0x138 RSRVD DYN_DDLY_CH9[2:0]
0x139 RSRVD DYN_DDLY_CH10[2:0]
0x13A RSRVD DYN_DDLY_CH11[2:0]
0x13B RSRVD DYN_DDLY_CH12[2:0]
0x13C RSRVD DYN_DDLY_CH13[2:0]
0x13D RSRVD DYN_DDLY_CH14[2:0]
0x13E RSRVD DYN_DDLY_CH15[2:0]
0x140 RSRVD OUTCH_SYSREF_PLSCNT[5:0]
0x141 SYNC_INT_MUX[7:0]
0x142 RSRVD SYNC_OUTPUT_HIZ SYNC_ENB_INSTAGE SYNC_EN_ML_INSTAGE RSRVD SYNC_OUTPUT_DATA SYNC_INPUT_Y12 SYNC_INPUT_M12
0x143 RSRVD FBBUF_CH6_EN RSRVD FBBUF_CH9_EN
0x146 RSRVD PLL2_NBYPASS_DIV2_FB PLL2_PRESCALER[3:0] PLL2_FBDIV_MUXSEL[1:0]
0x149 RSRVD PLL1_CLKINSEL1_ML_HOLDOVER PLL1_SYNC_HOLDOVER PLL1_STATUS1_HOLDOVER PLL1_STATUS0_HOLDOVER
0x14A RSRVD SYNC_ANALOGDLY[4:0] SYNC_ANALOGDLY_EN SYNC_INV
0x14B DYN_DDLY_CH15_EN DYN_DDLY_CH14_EN DYN_DDLY_CH13_EN DYN_DDLY_CH12_EN DYN_DDLY_CH11_EN DYN_DDLY_CH10_EN DYN_DDLY_CH9_EN DYN_DDLY_CH8_EN
0x14C DYN_DDLY_CH7_EN DYN_DDLY_CH6_EN DYN_DDLY_CH5_EN DYN_DDLY_CH4_EN DYN_DDLY_CH3_EN DYN_DDLY_CH2_EN DYN_DDLY_CH1_EN DYN_DDLY_CH0_EN
0x14E SYSREF_EN_CH14_15 SYSREF_EN_CH12_13 SYSREF_EN_CH10_11 SYSREF_EN_CH8_9 SYSREF_EN_CH6_7 SYSREF_EN_CH4_5 SYSREF_EN_CH2_3 SYSREF_EN_CH0_1
0x150 RSRVD PLL2_PFD_DIS_SAMPLE PLL2_PROG_PFD_RESET[2:0]
0x151 RSRVD PLL2_RFILT RSRVD PLL2_CP_EN_SAMPLE_BYP PLL2_CPROP[1:0]
0x152 RSRVD PLL2_EN_FILTER PLL2_CSAMPLE[2:0]
0x153 RSRVD PLL2_CFILT