JAJSDF8B March 2017 – July 2019 LMK04616
PRODUCTION DATA.
The OUTCH23CNTRL1 Register controls Output CH2_3 Back to Register Map.
BIT NO. | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
[7:2] | OUTCH3_DRIV_MODE[5:0] | RW | 0x18 | OUTCH3 Clock Driver Mode Setting. See CHANNEL0 for description. |
[1] | DIV_DCC_EN_CH2_3 | RW | 1 | Output CH2_3 Divider Duty Cycle Correction Enable |
[0] | OUTCH23_DIV_CLKEN | RW | 1 | OUTCH23 Channel Divider Clock Enable. Enables output channel PLL Clock Buffer. |