JAJSDF8B March 2017 – July 2019 LMK04616
PRODUCTION DATA.
The OUTCH45CNTRL1 Register controls Output CH4_5 Back to Register Map.
BIT NO. | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
[7:2] | OUTCH5_DRIV_MODE[5:0] | RW | 0x18 | OUTCH5 Clock Driver Mode Setting. |
[1] | DIV_DCC_EN_CH4_5 | RW | 1 | Output CH4_5 Divider Duty Cycle Correction Enable |
[0] | OUTCH45_DIV_CLKEN | RW | 1 | OUTCH45 Channel Divider Clock Enable. Enables output channel PLL Clock Buffer. |