JAJSDF8B March 2017 – July 2019 LMK04616
PRODUCTION DATA.
The OUTCH1011CNTRL1 Register controls Output CH10_11 Back to Register Map.
BIT NO. | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
[7:2] | OUTCH11_DRIV_MODE[5:0] | RW | 0x18 | OUTCH11 Clock Driver Mode Setting. |
[1] | DIV_DCC_EN_CH10_11 | RW | 0 | Output CH10_11 Divider Duty Cycle Correction Enable |
[0] | OUTCH1011_DIV_CLKEN | RW | 1 | OUTCH1011 Channel Divider Clock Enable. Enables output channel PLL Clock Buffer. |