When there are multiple devices that can satisfy the frequency requirement, performance characteristics can sometimes be used to make a decision. Consider the following example of where an output frequency of 1200 to 1250 MHz is desired with a channel spacing of 100 kHz. From the frequency table, the LMX2541SQ2380E could be used with a divide value of 2, or the LMX2541SQ3740E option could be used with a divide value of 3. This raises the question: Which one has better performance? The following table is helpful in comparing the performance.

Considering the fractional spurs and phase noise, the channel spacing at the 2380E VCO would be 200 kHz. When this is divided by two, the offset of these spurs does not change and the spurs at the VCO output would be reduced by a factor of 20·log(2) = 6 dB. The channel spacing at the 3740E VCO would be 300 kHz and these spurs would be reduced by a factor of 20·log(3) = 9.5 dB. So the spurs of the 3740E option would probably be better by virtue of the fact that they are farther from the carrier and easier to filter and also that they are divided down more by the VCO divider. The fractional phase noise would also be (9.5 - 6) = 3.5 dB better by the same reasoning.

Now consider the VCO phase noise. For the 3740E option, 1200 - 1250 MHz corresponds to a VCO frequency of 3600 - 3750 MHz, which is closer to the lower end of the tuning range for this device. For the 2380E option, this would correspond to 2400 - 2500 MHz, which is closer to the higher end of the tuning range. To verify this, take the phase noise numbers from the electrical specifications, extrapolate them to the actual frequencies, and then subtract a factor of 20·log(VCO_DIV). For the 2380E option, this works out to -116 dBc/Hz at 1200 MHz and -115.4 dBc/Hz at 1250 MHz. For the 3740E option, this works out to -117.4 dBc/Hz at 1200 MHz and -116.9 dBc/Hz at 1250 MHz.

10.1.3.1 PLL Phase Noise Measurement

To get an accurate measurement of the PLL phase noise, one needs to ensure four things.

• The PLL loop bandwidth is sufficiently wide so that the VCO noise does not degrade the measurement
• The measurement is not corrupted by peaking in the loop filter response.
• The reference source is sufficiently clean so that this does not degrade the measurement.
• A distinction is made between the PLL flat noise and the PLL 1/f noise

If the PLL loop bandwidth is made as wide as possible, then this helps keep the peaking of the loop filter response and the VCO noise from degrading the measurement. For the ultimate accuracy, this loop filter response can be factored into the measurement. As for the cleanliness of the reference source, the best sources tend to be those that are fixed, such as a 100 MHz Wenzel oscillator. Signal generators tend to be noisy, but if that is all that is available, then there are a few things that can help compensate for this. One technique is to use a higher frequency and divide this down to a lower frequency. For instance, a 500 MHz signal divided down to 20 MHz typically has much better phase noise than a direct 20 MHz signal, if it comes from a signal generator. Another technique is to measure the noise of the reference source and then multiply it up and then subtract it from the measurement. For instance, if the signal source was 500 MHz and the output frequency was 4 GHz, this signal source noise would be multiplied up by a factor of 20·log(4 GHz / 500 MHz) = 18 dB. Once that is done, the 1/f noise and the flat noise can be measured.

10.1.3.2 VCO Phase Noise Measurement

In order to measure the VCO phase noise, the loop filter resistors should be set to their minimum value to reduce their noise contribution. The loop bandwidth should also be made as narrow as possible. Because the loop bandwidth is very narrow, the cleanliness of the OSCin signal is therefore not as important. The phase noise is measured outside the loop bandwidth of the system.

An alternative way that might not be as accurate, but is much easier to do is to lock the device to a frequency and then set the CPT bit to 1 to disable the charge pump. The VCO will drift a little, the averaging on the equipment should be reset after this bit is changed and one cannot take to long to take this measurement. Test equipment that tracks the signal source is better if using this open loop technique.

10.1.3.3 Divider Phase Noise Measurement

The basic method for measuring the divider noise is to drive the divider with a noise source of known value and then subtract away this noise. The divider noise floor tends to be flat, whereas the VCO phase noise decreases with offset frequency, so this measurement is made at as far of an offset that is possible. When using Internal VCO Mode (MODE=0), the raw VCO phase noise with VCO_DIV=1 can be measured. Then the VCO divider can be programmed to get close to the desired frequency. For example, the VCO frequency can be set to 4 GHz and the phase noise measured. This phase noise data can be saved or downloaded. Suppose then that one was interested in the divider noise at 400 MHz. The VCO divider could be set to 10 and then 20 dB is subtracted from the VCO phase noise to figure its contribution at 400 MHz. Provided that the actual phase noise measured at 400 MHz with VCO_DIV is above this, then one can assume that this is the noise of the divider.

An alternative way to measure this is to drive the OSCin pin and use Divider Only (MODE=2) to measure the phase noise. This gives direct control of the frequency, but one should be sure that the noise being measured is the device and not the frequency source.

10.1.4.1 OSCin Input Impedance Measurement

For this pin, the provided calibration standards are typically good enough for a decent measurement. A single-ended measurement at the OSCin or OSCin* pins can be made For a differential measurement, this needs to be treated by the instrument as a two port network.

10.1.4.2 ExtVCOin Input Impedance Measurement

Because this pin goes higher in frequency, it is often difficult get a good measurement at higher frequencies because of the effects of the board and SMA connector. One technique that can be used is instead of using the provided calibration standards that come with the equipment, solder resistors directly to the board in order to calibrate out the effects of the board as well. A 0 ohm resistor functions as a short, no resistor functions as an open, and two parallel 100 ohm resistors serve as a load. These should be soldered as close to the part as possible. Once this calibration is done, the measurement can be done as normal.

10.1.4.3 RFout Output Impedance Measurement

Although output and input impedance are not the same thing, they can be measured in a similar way. Because this pin is a higher frequency, it is better to use the same method for calibration as used for the ExtVCOin pin. The other consideration for the RFout pin is that there are many different settings that impact this input impedance. When in bypass mode (VCO_DIV=1), the VCOGAIN and OUTTERM words can change the impedance. When in divided mode (VCO_DIV>1), the DIVGAIN and OUTTERM words can impact the impedance.

10.1.6.1 Input Sensitivity Test Procedure

There are two things that are important to consider when measuring the OSCin sensitivity.

• The action of setting the Ftest/LD pin to monitor the R divider output degrades the OSCin sensitivity.
• The internal VCO frequency calibration is based on the OSCin signal

Because of these considerations, the OSCin sensitivity needs to be measured in a closed loop test in such a way that the internal frequency calibration is not distorting the measurement. To do this, a known frequency and power level are set at the OSCin pin and the power level is changed until the PLL becomes more than 1 ppm off frequency. The PLL_R divider is varied to maintain a phase detector frequency of 1 MHz to ensure that the PLL loop does not become unstable. The frequency counter needs to be synchronized in frequency to the signal generator. It is better to use a narrower loop bandwidth for this test because the phase noise of the PLL might degrade when the OSCin power level gets to close to the sensitivity limits. Typically, a 0.1 uF capacitor is used as a DC block for the signal at the OSCin pin. The sensitivity at the OSCin pin is measured with a single-ended input.

This test can be run in internal VCO mode (MODE=0) or external VCO mode (MODE=1). When doing the test in internal VCO mode, the part needs to be initially locked and then the R counter is programmed to adjust for the OSCin frequency. However, in internal VCO mode, the PLL_N counter cannot be programmed, because the action of programming this counter activates the internal VCO frequecy calibration, which can interfere with the test.

10.1.6.2 OSCin Slew Rate Tests

There are two methods that can be used to test the OSCin slew rate. One method is to use test equipment that actually allows the user to vary the slew rate directly, but this type of equipment typically does not give the user enough range of adjustability. Another method is to calculate the slew rate based on the slope of a sine wave of known frequency and amplitude. For this method, the slew rate can be calculated from the frequency and peak to peak amplitude of the OSCin signal as follows: Slew_OSCin = 2 × π × f_OSCin × Vpp_OSCin

10.1.7.3 OSCin/OSCin* Connections

For single-ended operation, the signal is driven into the OSCin pin. The OSCin* pin is terminated the same as the OSCin pin. This is a typical case if the device is driven by a TCXO. For both single-ended and differential operation, the input is AC coupled because the OSCin/OSCin* pins self-bias to an optimal DC operating point. Better performance for both phase noise and fractional spurs is obtained for signals with a higher slew rate, such as a square wave. This is especially important for lower frequency signals, because slower frequency sine waves have lower slew rates. Fractional spurs are typically about four dB better when running in differential mode as opposed to single-ended mode.

10.1.7.3.1 Single-Ended Operation

For differential operation, as is the case when using an LVDS or LVPECL driver, a 100 Ω resistor is placed across the OSCin/OSCin* traces

10.1.7.3.2 Differential Operation

A third way to configure the device is in crystal mode (XO = 1). For this, the crystal is placed across the OSCin/OSCin* pins. Crystals are specified for a specific load capacitance, C_Load. The load capacitors shown in the figure each have a value of C_Load/2.

10.1.7.3.3 Crystal Mode Operation

Table 19. Design Parameters