JAJSB44G October   2011  – July 2018 LMZ10500

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      VIN = 3.6Vでの標準的な効率
      2.      放射EMI (CISPR22) VIN = 5V、VOUT = 1.8V、IOUT = 650mA
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Current Limit
      2. 7.3.2 Start-up Behavior and Soft Start
      3. 7.3.3 Output Short Circuit Protection
      4. 7.3.4 Thermal Overload Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Circuit Operation
      2. 7.4.2 Input Undervoltage Detection
      3. 7.4.3 Shutdown Mode
      4. 7.4.4 EN Pin Operation
      5. 7.4.5 Internal Synchronous Rectification
      6. 7.4.6 High Duty Cycle Operation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting the Output Voltage
          1. 8.2.2.2.1 RT and RB Selection for Fixed VOUT
          2. 8.2.2.2.2 Output Voltage Accuracy Optimization
        3. 8.2.2.3 Dynamic Output Voltage Scaling
        4. 8.2.2.4 Integrated Inductor
        5. 8.2.2.5 Input and Output Capacitor Selection
      3. 8.2.3 Application Curves
        1. 8.2.3.1 VOUT = 1.2 V
        2. 8.2.3.2 VOUT = 1.8 V
        3. 8.2.3.3 VOUT = 2.5 V
        4. 8.2.3.4 VOUT = 3.3 V
  9. Power Supply Recommendations
    1. 9.1 Voltage Range
    2. 9.2 Current Capability
    3. 9.3 Input Connection
      1. 9.3.1 Voltage Drops
      2. 9.3.2 Stability
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Package Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントのサポート
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • SIL|8
発注情報

Output Voltage Accuracy Optimization

Each nano module is optimized to achieve high VOUT accuracy. Equation 1 shows that, by design, the output voltage is a function of the VCON voltage and the gain from VCON to VFB. The voltage at VCON is derived from VREF. Therefore, as shown in Equation 3, the accuracy of the output voltage is a function of the VREF × GAIN product as well as the tolerance of the RT and RB resistors. The typical VREF × GAIN product by design is 5.875V. Each nano module's VREF voltage is trimmed so that this product is as close to the ideal 5.875V value as possible, achieving high VOUT accuracy. See Electrical Characteristics for the VREF × GAIN product tolerance limits.