JAJSFM8B June   2018  – May 2019 LMZM33606

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     概略回路図
  3. 3 概要
    1.     最小のソリューション・サイズ
    2.     標準的な効率(自動モード)
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics (VIN = 12 V)
    8. 6.8 Typical Characteristics (VIN = 24 V)
    9. 6.9 Typical Characteristics (VIN = 36 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage
      2. 7.3.2  Input Capacitor Selection
      3. 7.3.3  Output Capacitor Selection
      4. 7.3.4  Transient Response
      5. 7.3.5  Feed-Forward Capacitor
      6. 7.3.6  Switching Frequency (RT)
      7. 7.3.7  Synchronization (SYNC/MODE)
      8. 7.3.8  Output Enable (EN)
      9. 7.3.9  Programmable System UVLO (EN)
      10. 7.3.10 Internal LDO and BIAS_SEL
      11. 7.3.11 Power Good (PGOOD) and Power Good Pull-Up (PGOOD_PU)
      12. 7.3.12 Mode Select (Auto or FPWM)
      13. 7.3.13 Soft Start and Voltage Tracking
      14. 7.3.14 Voltage Dropout
      15. 7.3.15 Overcurrent Protection (OCP)
      16. 7.3.16 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Auto Mode
      3. 7.4.3 FPWM Mode
      4. 7.4.4 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Setpoint
        2. 8.2.2.2 Setting the Switching Frequency
        3. 8.2.2.3 Input Capacitors
        4. 8.2.2.4 Output Capacitor Selection
        5. 8.2.2.5 Feed-Forward Capacitor (CFF)
        6. 8.2.2.6 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Theta JA vs PCB Area
    4. 10.4 Package Specifications
    5. 10.5 EMI
      1. 10.5.1 EMI Plots
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報
    1. 12.1 Tape and Reel Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RLX|41
サーマルパッド・メカニカル・データ
発注情報

7.3.10 Internal LDO and BIAS_SEL

The LMZM33606 integrates an internal LDO, generating a typical VCC voltage (3.27 V) for control circuitry and MOSFET drivers. The LDO generates VCC voltage from VIN unless a sufficient bias voltage, VBIAS, is applied to BIAS_SEL pin. The BIAS_SEL input provides an option to supply the LDO with a lower voltage than VIN to reduce the LDO power loss. The smaller the difference between the input applied to the LDO, VIN_LDO, and the LDO output voltage, VCC, the more efficiently the device will perform. The amount of current supplied through the LDO will change based on operating conditions. Figure 36 demonstrates the typical LDO current, ILDO, for common input voltages over the recommended switching frequency range.

LMZM33606 LMZM3360x_FSWvsInternalLDOCurrent.gif
VOUT = 5 V
Figure 36. LDO Current vs Switching Frequency

The amount of power loss in the LDO can be calculated by Equation 4.

Equation 4. LMZM33606 PLossLDO_Eq.gif

For example, when the device is operating at VIN = 24 V, VOUT = 5 V, fsw = 500 kHz, BIAS_SEL = PGND, the ILDO is typical 11 mA, therefore, the PLOSS_LDO = 11 mA × (24 V – 3.27 V) = 228.03 mW. For the same operating conditions with BIAS_SEL = 5 V, the power loss is equal to 11 mA × (5 V – 3.27 V) = 19.03 mW. The benefits of applying a bias voltage to reduce power loss are most notable in applications when VIN » VCC or when the device is operating at a higher switching frequency. The power savings can be calculated by Equation 5.

Equation 5. LMZM33606 PowerSavings_Eq.gif

Figure 37 and Figure 38 show efficiency plots of the LMZM33606 operating with different source voltages applied to the BIAS_SEL pin. Figure 39 demonstrates the power dissipation of the device with various source voltages at BIAS_SEL pin. The plots include BIAS_SEL tied to a 3.3 V external bias, 5 V external bias, VOUT (5 V) and no bias voltage applied. The efficiency improvements are more significant when the device is operating at light loads because the LDO loss is a higher percentage of the total loss.

LMZM33606 LMZM33606_LoadEfficiencywithBIAS_SEL_24Vin5Vout.gif
VIN = 24 V fSW = 500 kHz FPWM Mode
Figure 37. Efficiency Comparison with BIAS_SEL vs Output Current
LMZM33606 LMZM33606_PowerDissipationwithBIAS_SEL_24Vin5Vout.gif
VIN = 24 V fSW = 500 kHz FPWM Mode
Figure 39. Power Dissipation Comparison with BIAS_SEL
LMZM33606 LMZM33606_LoadEfficiencywithBIAS_SEL_24Vin5Vout_LogScale.gif
VIN = 24 V fSW = 500 kHz FPWM Mode
Figure 38. Efficiency Comparison with BIAS_SEL vs Output Current