JAJSFS9R August   2010  – September 2018 MSP430F5131 , MSP430F5132 , MSP430F5151 , MSP430F5152 , MSP430F5171 , MSP430F5172

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics
    7. 5.7  Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.5, P3.2 to P3.7, and PJ.0 to PJ.6)
    8. 5.8  Schmitt-Trigger Inputs – General-Purpose I/O (P1.6 and P1.7, P2.0 to P2.7, and P3.0 and P3.1)
    9. 5.9  Inputs – Ports P1 and P2
    10. 5.10 Leakage Current – General-Purpose I/O
    11. 5.11 Outputs – Ports P1, P3, PJ (Full Drive Strength, P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6)
    12. 5.12 Outputs – Ports P1 to P3 (Full Drive Strength, P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1)
    13. 5.13 Outputs – Ports P1, P3, PJ (Reduced Drive Strength, P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6)
    14. 5.14 Outputs – Ports P1 to P3 (Reduced Drive Strength, P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1)
    15. 5.15 Output Frequency – Ports P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6
    16. 5.16 Output Frequency – Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1
    17. 5.17 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0), Ports P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6
    18. 5.18 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1), Ports P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6
    19. 5.19 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0), Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1
    20. 5.20 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1), Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1
    21. 5.21 Crystal Oscillator, XT1, Low-Frequency Mode
    22. 5.22 Crystal Oscillator, XT1, High-Frequency Mode
    23. 5.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    24. 5.24 Internal Reference, Low-Frequency Oscillator (REFO)
    25. 5.25 DCO Frequency
    26. 5.26 PMM, Brownout Reset (BOR)
    27. 5.27 PMM, Core Voltage
    28. 5.28 PMM, SVS High Side
    29. 5.29 PMM, SVM High Side
    30. 5.30 PMM, SVS Low Side
    31. 5.31 PMM, SVM Low Side
    32. 5.32 Wake-up Times From Low-Power Modes
    33. 5.33 Timer_A
    34. 5.34 USCI (UART Mode)
    35. 5.35 USCI (SPI Master Mode)
    36. 5.36 USCI (SPI Slave Mode)
    37. 5.37 USCI (I2C Mode)
    38. 5.38 10-Bit ADC, Power Supply and Input Range Conditions (MSP430F51x2 Devices Only)
    39. 5.39 10-Bit ADC, Timing Parameters (MSP430F51x2 Devices Only)
    40. 5.40 10-Bit ADC, Linearity Parameters (MSP430F51x2 Devices Only)
    41. 5.41 REF, External Reference (MSP430F51x2 Devices Only)
    42. 5.42 REF, Built-In Reference (MSP430F51x2 Devices Only)
    43. 5.43 Comparator_B
    44. 5.44 Timer_D, Power Supply and Reference Clock
    45. 5.45 Timer_D, Local Clock Generator Frequency
    46. 5.46 Timer_D, Trimmed Clock Frequencies
    47. 5.47 Timer_D, Frequency Multiplication Mode
    48. 5.48 Timer_D, Input Capture and Output Compare Timing
    49. 5.49 Flash Memory
    50. 5.50 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  Flash Memory
    8. 6.8  RAM
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O
      2. 6.9.2  Port Mapping Controller
      3. 6.9.3  Oscillator and System Clock
      4. 6.9.4  Power-Management Module (PMM)
      5. 6.9.5  Hardware Multiplier
      6. 6.9.6  Watchdog Timer (WDT_A)
      7. 6.9.7  System Module (SYS)
      8. 6.9.8  DMA Controller
      9. 6.9.9  Universal Serial Communication Interface (USCI)
      10. 6.9.10 TA0
      11. 6.9.11 TD0
      12. 6.9.12 TD1
      13. 6.9.13 Comparator_B
      14. 6.9.14 ADC10_A (MSP430F51x2 Only)
      15. 6.9.15 CRC16
      16. 6.9.16 Reference (REF) Module Voltage Reference
      17. 6.9.17 Embedded Emulation Module (EEM) (S Version)
      18. 6.9.18 Peripheral File Map
    10. 6.10 Input/Output Diagrams
      1. 6.10.1  Port P1 (P1.0 to P1.5) Input/Output With Schmitt Trigger
      2. 6.10.2  Port P1 (P1.6 to P1.7) Input/Output With Schmitt Trigger
      3. 6.10.3  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      4. 6.10.4  Port P3 (P3.0 and P3.1) Input/Output With Schmitt Trigger
      5. 6.10.5  Port P3 (P3.2 and P3.3) Input/Output With Schmitt Trigger
      6. 6.10.6  Port P3 (P3.4) Input/Output With Schmitt Trigger
      7. 6.10.7  Port P3 (P3.5) Input/Output With Schmitt Trigger
      8. 6.10.8  Port P3 (P3.6) Input/Output With Schmitt Trigger
      9. 6.10.9  Port P3 (P3.7) Input/Output With Schmitt Trigger
      10. 6.10.10 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      11. 6.10.11 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
      12. 6.10.12 Port J (PJ.4) Input/Output With Schmitt Trigger
      13. 6.10.13 Port J (PJ.5) Input/Output With Schmitt Trigger
      14. 6.10.14 Port J (PJ.6) Input/Output With Schmitt Trigger
    11. 6.11 Device Descriptors
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1  使い始めと次の手順
    2. 7.2  Device Nomenclature
    3. 7.3  ツールとソフトウェア
    4. 7.4  ドキュメントのサポート
    5. 7.5  関連リンク
    6. 7.6  Community Resources
    7. 7.7  商標
    8. 7.8  静電気放電に関する注意事項
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC Supply voltage during program execution and flash programming
V(AVCC)  = V(DVCC)  = VCC(1)(2) 		PMMCOREVx = 0 1.8 3.6 V
PMMCOREVx = 0, 1 2.0 3.6
PMMCOREVx = 0, 1, 2 2.2 3.6
PMMCOREVx = 0, 1, 2, 3 2.4 3.6
VIO Supply voltage of pins P1.6, P1.7, P2.0 to P2.7, P3.0, and P3.1 supplied by VIO(4)(7) 1.8 5.5 V
VSS Supply voltage V(AVSS)  = V(DVSS) = VSS 0 V
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature –40 85 °C
C(VCORE) Recommended capacitor at VCORE(3) 470 nF
C(DVCC)/
C(VCORE) 		Capacitor ratio of DVCC to VCORE 10
fSYSTEM Processor frequency (maximum MCLK frequency)(5)(6) (see Figure 5-1) PMMCOREVx = 0, 1.8 V ≤ VCC ≤ 3.6 V (default condition) 0 12 MHz
PMMCOREVx = 1, 2.0 V ≤ VCC ≤ 3.6 V 0 16
PMMCOREVx = 2, 2.2 V ≤ VCC ≤ 3.6 V 0 20
PMMCOREVx = 3, 2.4 V ≤ VCC ≤ 3.6 V 0 25
PINT Internal power dissipation VCC × I(DVCC) W
PIO I/O power dissipation of the I/O pins powered by DVCC (VCC – VIOH) × IIOH +
VIOL × IIOL 		W
PIO5 I/O power dissipation of the I/O pins powered by VIO (VIO – VIOH5) × IIOH5 +
VIOL5 × IIOL5 		W
PMAX Maximum allowed power dissipation, PMAX > PIO + PIO5 + PINT (TJ – TA) / RθJA W
(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between V(AVCC) and V(DVCC) can be tolerated during power up and operation.
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Section 5.28 threshold parameters for the exact values and further details.
(3) A capacitor tolerance of ±20% or better is required.
(4) If DVIO is not supplied by the same source as DVCC, TI recommends powering AVCC and DVCC before powering DVIO. At DVCC and AVCC voltages higher than 1.8 V, the maximum difference of 0.3 V between DVIO and (DVCC and AVCC) can be exceeded. DVIO must be higher than or equal to DVCC.
Increased cross current can flow into DVCC if DVIO is less than (DVCC – 0.3 V), with a maximum current flowing when DVIO is equal to DVCC/2. To avoid high currents into DVCC, DVIO must be higher than or equal to DVCC, DVIO must not float, and DVIO must be turned off quickly. TI recommends pulling the DVIO pins to low before disabling DVIO.
(5) The MSP430™ CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the specified maximum frequency.
(6) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(7) For best cross-current prevention, voltage applied to DVIO should not be lower than DVCC. However, if DVIO is switched off during operation, due to application requirements, DVIO should be pulled to ground to prevent a floating voltage.
MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131 slas619-r-041.gifFigure 5-1 Frequency vs Supply Voltage