JAJSG78F July   2011  – September 2018 MSP430F5340 , MSP430F5341 , MSP430F5342

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics, VQFN (RGZ) Package
    7. 5.7  Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3, RST/NMI)
    8. 5.8  Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
    9. 5.9  Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3, RST/NMI)
    10. 5.10 Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
    11. 5.11 Outputs – General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
    12. 5.12 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
    13. 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    15. 5.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 5.16 Crystal Oscillator, XT2
    17. 5.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    18. 5.18 Internal Reference, Low-Frequency Oscillator (REFO)
    19. 5.19 DCO Frequency
    20. 5.20 PMM, Brownout Reset (BOR)
    21. 5.21 PMM, Core Voltage
    22. 5.22 PMM, SVS High Side
    23. 5.23 PMM, SVM High Side
    24. 5.24 PMM, SVS Low Side
    25. 5.25 PMM, SVM Low Side
    26. 5.26 Wake-up Times From Low-Power Modes and Reset
    27. 5.27 Timer_A
    28. 5.28 Timer_B
    29. 5.29 USCI (UART Mode) Clock Frequency
    30. 5.30 USCI (UART Mode)
    31. 5.31 USCI (SPI Master Mode) Clock Frequency
    32. 5.32 USCI (SPI Master Mode)
    33. 5.33 USCI (SPI Slave Mode)
    34. 5.34 USCI (I2C Mode)
    35. 5.35 12-Bit ADC, Power Supply and Input Range Conditions
    36. 5.36 12-Bit ADC, Timing Parameters
    37. 5.37 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
    38. 5.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    39. 5.39 12-Bit ADC, Temperature Sensor and Built-In VMID
    40. 5.40 REF, External Reference
    41. 5.41 REF, Built-In Reference
    42. 5.42 Comparator_B
    43. 5.43 Flash Memory
    44. 5.44 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Operating Modes
    3. 6.3  Interrupt Vector Addresses
    4. 6.4  Memory Organization
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  Flash Memory
    8. 6.8  RAM
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O
      2. 6.9.2  Port Mapping Controller
      3. 6.9.3  Oscillator and System Clock
      4. 6.9.4  Power Management Module (PMM)
      5. 6.9.5  Hardware Multiplier
      6. 6.9.6  Real-Time Clock (RTC_A)
      7. 6.9.7  Watchdog Timer (WDT_A)
      8. 6.9.8  System Module (SYS)
      9. 6.9.9  DMA Controller
      10. 6.9.10 Universal Serial Communication Interface (USCI)
      11. 6.9.11 TA0
      12. 6.9.12 TA1
      13. 6.9.13 TA2
      14. 6.9.14 TB0
      15. 6.9.15 Comparator_B
      16. 6.9.16 ADC12_A
      17. 6.9.17 CRC16
      18. 6.9.18 Reference (REF) Module Voltage Reference
      19. 6.9.19 Embedded Emulation Module (EEM)
      20. 6.9.20 Peripheral File Map
    10. 6.10 Input/Output Diagrams
      1. 6.10.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.10.2  Port P2 (P2.7) Input/Output With Schmitt Trigger
      3. 6.10.3  Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger
      4. 6.10.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 6.10.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 6.10.6  Port P5 (P5.2) Input/Output With Schmitt Trigger
      7. 6.10.7  Port P5 (P5.3) Input/Output With Schmitt Trigger
      8. 6.10.8  Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
      9. 6.10.9  Port P5 (P5.7) Input/Output With Schmitt Trigger
      10. 6.10.10 Port P6 (P6.1 to P6.5) Input/Output With Schmitt Trigger
      11. 6.10.11 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      12. 6.10.12 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 6.11 Device Descriptors
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1  はじめに
    2. 7.2  Device Nomenclature
    3. 7.3  ツールとソフトウェア
    4. 7.4  ドキュメントのサポート
    5. 7.5  関連リンク
    6. 7.6  Community Resources
    7. 7.7  商標
    8. 7.8  静電気放電に関する注意事項
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4.2 Signal Descriptions

Table 4-1 describes the signals.

Table 4-1 Signal Descriptions

TERMINAL I/O(1) DESCRIPTION
NAME NO.
P6.3/CB3/A3 1 I/O General-purpose digital I/O

Comparator_B input CB3

Analog input A3 for the ADC
P6.4/CB4/A4 2 I/O General-purpose digital I/O

Comparator_B input CB4

Analog input A4 for the ADC
P6.5/CB5/A5 3 I/O General-purpose digital I/O

Comparator_B input CB5

Analog input A5 for the ADC
P5.0/A8/VREF+/VeREF+ 4 I/O General-purpose digital I/O

Analog input A8 for the ADC

Output of reference voltage to the ADC

Input for an external reference voltage to the ADC
P5.1/A9/VREF-/VeREF- 5 I/O General-purpose digital I/O

Analog input A9 for the ADC

Negative terminal for the ADC reference voltage for both sources, the internal reference voltage, or an external applied reference voltage
AVCC1 6 Analog power supply
P5.4/XIN 7 I/O General-purpose digital I/O

Input terminal for crystal oscillator XT1
P5.5/XOUT 8 I/O General-purpose digital I/O

Output terminal of crystal oscillator XT1
AVSS1 9 Analog ground supply
DVCC1 10 Digital power supply
DVSS1 11 Digital ground supply
VCORE(2) 12 Regulated core power supply output (internal use only, no external current loading)
P1.0/TA0CLK/ACLK 13 I/O General-purpose digital I/O with port interrupt

TA0 clock signal TA0CLK input

ACLK output (divided by 1, 2, 4, 8, 16, or 32)
P1.1/TA0.0 14 I/O General-purpose digital I/O with port interrupt

TA0 CCR0 capture: CCI0A input, compare: Out0 output

BSL transmit output
P1.2/TA0.1 15 I/O General-purpose digital I/O with port interrupt

TA0 CCR1 capture: CCI1A input, compare: Out1 output

BSL receive input
P1.3/TA0.2 16 I/O General-purpose digital I/O with port interrupt

TA0 CCR2 capture: CCI2A input, compare: Out2 output
P1.4/TA0.3 17 I/O General-purpose digital I/O with port interrupt

TA0 CCR3 capture: CCI3A input compare: Out3 output
P1.5/TA0.4 18 I/O General-purpose digital I/O with port interrupt

TA0 CCR4 capture: CCI4A input, compare: Out4 output
P1.6/TA1CLK/CBOUT 19 I/O General-purpose digital I/O with port interrupt

TA1 clock signal TA1CLK input

Comparator_B output
P1.7/TA1.0 20 I/O General-purpose digital I/O with port interrupt

TA1 CCR0 capture: CCI0A input, compare: Out0 output
P2.7/UCB0STE/UCA0CLK 21 I/O General-purpose digital I/O with port interrupt

Slave transmit enable for USCI_B0 SPI mode

Clock signal input for USCI_A0 SPI slave mode

Clock signal output for USCI_A0 SPI master mode
P3.0/UCB0SIMO/UCB0SDA 22 I/O General-purpose digital I/O

Slave in, master out for USCI_B0 SPI mode

I2C data for USCI_B0 I2C mode
P3.1/UCB0SOMI/UCB0SCL 23 I/O General-purpose digital I/O

Slave out, master in for USCI_B0 SPI mode

I2C clock for USCI_B0 I2C mode
P3.2/UCB0CLK/UCA0STE 24 I/O General-purpose digital I/O

Clock signal input for USCI_B0 SPI slave mode

Clock signal output for USCI_B0 SPI master mode

Slave transmit enable for USCI_A0 SPI mode
P3.3/UCA0TXD/UCA0SIMO 25 I/O General-purpose digital I/O

Transmit data for USCI_A0 UART mode

Slave in, master out for USCI_A0 SPI mode
P3.4/UCA0RXD/UCA0SOMI 26 I/O General-purpose digital I/O

Receive data for USCI_A0 UART mode

Slave out, master in for USCI_A0 SPI mode
P4.0/PM_UCB1STE/ PM_UCA1CLK 27 I/O General-purpose digital I/O with reconfigurable port mapping secondary function

Default mapping: Slave transmit enable for USCI_B1 SPI mode

Default mapping: Clock signal input for USCI_A1 SPI slave mode

Default mapping: Clock signal output for USCI_A1 SPI master mode
P4.1/PM_UCB1SIMO/ PM_UCB1SDA 28 I/O General-purpose digital I/O with reconfigurable port mapping secondary function

Default mapping: Slave in, master out for USCI_B1 SPI mode

Default mapping: I2C data for USCI_B1 I2C mode
P4.2/PM_UCB1SOMI/ PM_UCB1SCL 29 I/O General-purpose digital I/O with reconfigurable port mapping secondary function

Default mapping: Slave out, master in for USCI_B1 SPI mode

Default mapping: I2C clock for USCI_B1 I2C mode
P4.3/PM_UCB1CLK/ PM_UCA1STE 30 I/O General-purpose digital I/O with reconfigurable port mapping secondary function

Default mapping: Clock signal input for USCI_B1 SPI slave mode

Default mapping: Clock signal output for USCI_B1 SPI master mode

Default mapping: Slave transmit enable for USCI_A1 SPI mode
DVSS2 31 Digital ground supply
DVCC2 32 Digital power supply
P4.4/PM_UCA1TXD/ PM_UCA1SIMO 33 I/O General-purpose digital I/O with reconfigurable port mapping secondary function

Default mapping: Transmit data for USCI_A1 UART mode

Default mapping: Slave in, master out for USCI_A1 SPI mode
P4.5/PM_UCA1RXD/ PM_UCA1SOMI 34 I/O General-purpose digital I/O with reconfigurable port mapping secondary function

Default mapping: Receive data for USCI_A1 UART mode

Default mapping: Slave out, master in for USCI_A1 SPI mode
P4.6/PM_NONE 35 I/O General-purpose digital I/O with reconfigurable port mapping secondary function

Default mapping: no secondary function.
P4.7/PM_NONE 36 I/O General-purpose digital I/O with reconfigurable port mapping secondary function

Default mapping: no secondary function.
P5.7/TB0.1 37 I/O General-purpose digital I/O

TB0 CCR1 capture: CCI1A input, compare: Out1 output
DVSS3 38 Digital ground supply
P5.2/XT2IN 39 I/O General-purpose digital I/O

Input terminal for crystal oscillator XT2
P5.3/XT2OUT 40 I/O General-purpose digital I/O

Output terminal of crystal oscillator XT2
TEST/SBWTCK(3) 41 I Test mode pin – Selects 4-wire JTAG operation.

Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated
PJ.0/TDO(4) 42 I/O General-purpose digital I/O

JTAG test data output port
PJ.1/TDI/TCLK(4) 43 I/O General-purpose digital I/O

JTAG test data input or test clock input
PJ.2/TMS(4) 44 I/O General-purpose digital I/O

JTAG test mode select
PJ.3/TCK(4) 45 I/O General-purpose digital I/O

JTAG test clock
RST/NMI/SBWTDIO(3) 46 I/O Reset input active low(5)

Nonmaskable interrupt input

Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated.
P6.1/CB1/A1 47 I/O General-purpose digital I/O

Comparator_B input CB1

Analog input A1 for the ADC
P6.2/CB2/A2 48 I/O General-purpose digital I/O

Comparator_B input CB2

Analog input A2 for the ADC
Thermal Pad QFN package pad. TI recommends connecting to VSS.
(1) I = input, O = output, N/A = not available
(2) VCORE is for internal use only. No external current loading is possible. VCORE should be connected to only the recommended capacitor value, CVCORE.
(3) See Section 6.5 and Section 6.6 for use with BSL and JTAG functions
(4) See Section 6.6 for use with JTAG function.
(5) When this pin is configured as reset, the internal pullup resistor is enabled by default.