JAJSG45F June   2010  – September 2018 MSP430F5630 , MSP430F5631 , MSP430F5632 , MSP430F5633 , MSP430F5634 , MSP430F5635 , MSP430F5636 , MSP430F5637 , MSP430F5638

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics
    7. 5.7  Schmitt-Trigger Inputs – General-Purpose I/O
    8. 5.8  Inputs – Ports P1, P2, P3, and P4
    9. 5.9  Leakage Current – General-Purpose I/O
    10. 5.10 Outputs – General-Purpose I/O (Full Drive Strength)
    11. 5.11 Outputs – General-Purpose I/O (Reduced Drive Strength)
    12. 5.12 Output Frequency – Ports P1, P2, and P3
    13. 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    15. 5.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 5.16 Crystal Oscillator, XT2
    17. 5.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    18. 5.18 Internal Reference, Low-Frequency Oscillator (REFO)
    19. 5.19 DCO Frequency
    20. 5.20 PMM, Brownout Reset (BOR)
    21. 5.21 PMM, Core Voltage
    22. 5.22 PMM, SVS High Side
    23. 5.23 PMM, SVM High Side
    24. 5.24 PMM, SVS Low Side
    25. 5.25 PMM, SVM Low Side
    26. 5.26 Wake-up Times From Low-Power Modes and Reset
    27. 5.27 Timer_A, Timers TA0, TA1, and TA2
    28. 5.28 Timer_B, Timer TB0
    29. 5.29 Battery Backup
    30. 5.30 USCI (UART Mode)
    31. 5.31 USCI (SPI Master Mode)
    32. 5.32 USCI (SPI Slave Mode)
    33. 5.33 USCI (I2C Mode)
    34. 5.34 12-Bit ADC, Power Supply and Input Range Conditions
    35. 5.35 12-Bit ADC, Timing Parameters
    36. 5.36 12-Bit ADC, Linearity Parameters Using an External Reference Voltage
    37. 5.37 12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage
    38. 5.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    39. 5.39 12-Bit ADC, Temperature Sensor and Built-In VMID
    40. 5.40 REF, External Reference
    41. 5.41 REF, Built-In Reference
    42. 5.42 12-Bit DAC, Supply Specifications
    43. 5.43 12-Bit DAC, Linearity Specifications
    44. 5.44 12-Bit DAC, Output Specifications
    45. 5.45 12-Bit DAC, Reference Input Specifications
    46. 5.46 12-Bit DAC, Dynamic Specifications
    47. 5.47 12-Bit DAC, Dynamic Specifications (Continued)
    48. 5.48 Comparator_B
    49. 5.49 Ports PU.0 and PU.1
    50. 5.50 USB Output Ports DP and DM
    51. 5.51 USB Input Ports DP and DM
    52. 5.52 USB-PWR (USB Power System)
    53. 5.53 USB-PLL (USB Phase-Locked Loop)
    54. 5.54 Flash Memory
    55. 5.55 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Instruction Set
    4. 6.4  Operating Modes
    5. 6.5  Interrupt Vector Addresses
    6. 6.6  Memory
    7. 6.7  Bootloader (BSL)
      1. 6.7.1 USB BSL
      2. 6.7.2 UART BSL
    8. 6.8  JTAG Operation
      1. 6.8.1 JTAG Standard Interface
      2. 6.8.2 Spy-Bi-Wire Interface
    9. 6.9  Flash Memory (Link to User's Guide)
    10. 6.10 RAM (Link to User's Guide)
    11. 6.11 Backup RAM
    12. 6.12 Peripherals
      1. 6.12.1  Digital I/O (Link to User's Guide)
      2. 6.12.2  Port Mapping Controller (Link to User's Guide)
      3. 6.12.3  Oscillator and System Clock (Link to User's Guide)
      4. 6.12.4  Power-Management Module (PMM) (Link to User's Guide)
      5. 6.12.5  Hardware Multiplier (MPY) (Link to User's Guide)
      6. 6.12.6  Real-Time Clock (RTC_B) (Link to User's Guide)
      7. 6.12.7  Watchdog Timer (WDT_A) (Link to User's Guide)
      8. 6.12.8  System Module (SYS) (Link to User's Guide)
      9. 6.12.9  DMA Controller (Link to User's Guide)
      10. 6.12.10 Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
      11. 6.12.11 Timer TA0 (Link to User's Guide)
      12. 6.12.12 Timer TA1 (Link to User's Guide)
      13. 6.12.13 Timer TA2 (Link to User's Guide)
      14. 6.12.14 Timer TB0 (Link to User's Guide)
      15. 6.12.15 Comparator_B (Link to User's Guide)
      16. 6.12.16 ADC12_A (Link to User's Guide)
      17. 6.12.17 DAC12_A (Link to User's Guide)
      18. 6.12.18 CRC16 (Link to User's Guide)
      19. 6.12.19 Voltage Reference (REF) Module (Link to User's Guide)
      20. 6.12.20 USB Universal Serial Bus (Link to User's Guide)
      21. 6.12.21 Embedded Emulation Module (EEM) (Link to User's Guide)
      22. 6.12.22 Peripheral File Map
    13. 6.13 Input/Output Diagrams
      1. 6.13.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.13.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 6.13.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 6.13.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 6.13.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 6.13.6  Port P5 (P5.2 to P5.7) Input/Output With Schmitt Trigger
      7. 6.13.7  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      8. 6.13.8  Port P7 (P7.2) Input/Output With Schmitt Trigger
      9. 6.13.9  Port P7 (P7.3) Input/Output With Schmitt Trigger
      10. 6.13.10 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      11. 6.13.11 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger
      12. 6.13.12 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger
      13. 6.13.13 Port PU (PU.0/DP, PU.1/DM, PUR) USB Ports
      14. 6.13.14 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      15. 6.13.15 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    14. 6.14 Device Descriptors
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1  使い始めと次の手順
    2. 7.2  Device Nomenclature
    3. 7.3  ツールとソフトウェア
    4. 7.4  ドキュメントのサポート
    5. 7.5  関連リンク
    6. 7.6  Community Resources
    7. 7.7  商標
    8. 7.8  静電気放電に関する注意事項
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table 6-3). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 6-3 Interrupt Sources, Flags, and Vectors of MSP430F563x Configurations

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
System Reset
Power-Up, External Reset
Watchdog Time-out, Key Violation
Flash Memory Key Violation
WDTIFG, KEYV (SYSRSTIV)(1)(3) Reset 0FFFEh 63, highest
System NMI
PMM
Vacant Memory Access
JTAG Mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV)(1) (Non)maskable 0FFFCh 62
User NMI
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG, OFIFG, ACCVIFG, BUSIFG (SYSUNIV)(1)(3) (Non)maskable 0FFFAh 61
Comp_B Comparator B interrupt flags (CBIV)(1)(2) Maskable 0FFF8h 60
Timer TB0 TB0CCR0 CCIFG0(2) Maskable 0FFF6h 59
Timer TB0 TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
TB0IFG (TBIV)(1)(2)
Maskable 0FFF4h 58
Watchdog Interval Timer Mode WDTIFG Maskable 0FFF2h 57
USCI_A0 Receive or Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV)(1)(2) Maskable 0FFF0h 56
USCI_B0 Receive or Transmit UCB0RXIFG, UCB0TXIFG (UCB0IV)(1)(2) Maskable 0FFEEh 55
ADC12_A(5) ADC12IFG0 to ADC12IFG15 (ADC12IV)(1)(2) Maskable 0FFECh 54
Timer TA0 TA0CCR0 CCIFG0(2) Maskable 0FFEAh 53
Timer TA0 TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
TA0IFG (TA0IV)(1)(2)
Maskable 0FFE8h 52
USB_UBM USB interrupts (USBIV)(1)(2) Maskable 0FFE6h 51
DMA DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG, DMA4IFG, DMA5IFG (DMAIV)(1)(2) Maskable 0FFE4h 50
Timer TA1 TA1CCR0 CCIFG0(2) Maskable 0FFE2h 49
Timer TA1 TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG (TA1IV)(1)(2)
Maskable 0FFE0h 48
I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV)(1)(2) Maskable 0FFDEh 47
USCI_A1 Receive or Transmit UCA1RXIFG, UCA1TXIFG (UCA1IV)(1)(2) Maskable 0FFDCh 46
USCI_B1 Receive or Transmit UCB1RXIFG, UCB1TXIFG (UCB1IV)(1)(2) Maskable 0FFDAh 45
I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV)(1)(2) Maskable 0FFD8h 44
Reserved Reserved Maskable 0FFD6h 43
RTC_B RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV)(1)(2) Maskable 0FFD4h 42
DAC12_A(6) DAC12_0IFG, DAC12_1IFG(1)(2) Maskable 0FFD2h 41
Timer TA2 TA2CCR0 CCIFG0(2) Maskable 0FFD0h 40
Timer TA2 TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,
TA2IFG (TA2IV)(1)(2)
Maskable 0FFCEh 39
I/O Port P3 P3IFG.0 to P3IFG.7 (P3IV)(1)(2) Maskable 0FFCCh 38
I/O Port P4 P4IFG.0 to P4IFG.7 (P4IV)(1)(2) Maskable 0FFCAh 37
Reserved Reserved(4) 0FFC8h 36
0FF80h 0, lowest
Multiple source flags
Interrupt flags are in the module.
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatibility with other devices, TI recommends reserving these locations.
Only on devices with peripheral module ADC12_A, otherwise reserved.
Only on devices with peripheral module DAC12_A, otherwise reserved.