SLAS508J April   2006  – June 2015 MSP430FG4616 , MSP430FG4617 , MSP430FG4618 , MSP430FG4619

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3 Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Supply Current Into AVCC + DVCC Excluding External Current
    5. 5.5  Thermal Characteristics
    6. 5.6  Schmitt-Trigger Inputs - Ports P1 to P10, RST/NMI, JTAG (TCK, TMS, TDI/TCLK,TDO/TDI)
    7. 5.7  Inputs Px.x, TAx, TBX
    8. 5.8  Leakage Current - Ports P1 to P10
    9. 5.9  Outputs - Ports P1 to P10
    10. 5.10 Output Frequency
    11. 5.11 Typical Characteristics - Outputs
    12. 5.12 Wake-up Timing From LPM3
    13. 5.13 RAM
    14. 5.14 LCD_A
    15. 5.15 Comparator_A
    16. 5.16 Typical Characteristics - Comparator_A
    17. 5.17 POR, BOR
    18. 5.18 SVS (Supply Voltage Supervisor and Monitor)
    19. 5.19 DCO
    20. 5.20 Crystal Oscillator, LFXT1 Oscillator
    21. 5.21 Crystal Oscillator, XT2 Oscillator
    22. 5.22 USCI (UART Mode)
    23. 5.23 USCI (SPI Master Mode)
    24. 5.24 USCI (SPI Slave Mode)
    25. 5.25 USCI (I2C Mode)
    26. 5.26 USART1
    27. 5.27 12-Bit ADC, Power Supply and Input Range Conditions
    28. 5.28 12-Bit ADC, External Reference
    29. 5.29 12-Bit ADC, Built-In Reference
    30. 5.30 12-Bit ADC, Timing Parameters
    31. 5.31 12-Bit ADC, Linearity Parameters
    32. 5.32 12-Bit ADC, Temperature Sensor and Built-In VMID
    33. 5.33 12-Bit DAC, Supply Specifications
    34. 5.34 12-Bit DAC, Linearity Specifications
    35. 5.35 12-Bit DAC, Output Specifications
    36. 5.36 12-Bit DAC, Reference Input Specifications
    37. 5.37 12-Bit DAC, Dynamic Specifications
    38. 5.38 12-Bit DAC, Dynamic Specifications Continued
    39. 5.39 Operational Amplifier OA, Supply Specifications
    40. 5.40 Operational Amplifier OA, Input/Output Specifications
    41. 5.41 Operational Amplifier OA, Dynamic Specifications
    42. 5.42 Operational Amplifier OA, Typical Characteristics
    43. 5.43 Operational Amplifier OA Feedback Network, Noninverting Amplifier Mode (OAFCx = 4)
    44. 5.44 Operational Amplifier OA Feedback Network, Inverting Amplifier Mode (OAFCx = 6)
    45. 5.45 Flash Memory (FG461x Devices Only)
    46. 5.46 JTAG Interface
    47. 5.47 JTAG Fuse
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Special Function Registers (SFRs)
      1. 6.5.1 Interrupt Enable 1 and 2
      2. 6.5.2 Interrupt Flag Register 1 and 2
      3. 6.5.3 Module Enable Registers 1 and 2
    6. 6.6  Memory Organization
    7. 6.7  Bootstrap Loader (BSL)
    8. 6.8  Flash Memory
    9. 6.9  Peripherals
      1. 6.9.1  DMA Controller
      2. 6.9.2  Oscillator and System Clock
      3. 6.9.3  Brownout, Supply Voltage Supervisor (SVS)
      4. 6.9.4  Digital I/O
      5. 6.9.5  Basic Timer1 and Real-Time Clock
      6. 6.9.6  LCD_A Drive With Regulated Charge Pump
      7. 6.9.7  Watchdog Timer (WDT+)
      8. 6.9.8  Universal Serial Communication Interface (USCI)
      9. 6.9.9  USART1
      10. 6.9.10 Hardware Multiplier
      11. 6.9.11 Timer_A3
      12. 6.9.12 Timer_B7
      13. 6.9.13 Comparator_A
      14. 6.9.14 ADC12
      15. 6.9.15 DAC12
      16. 6.9.16 OA
      17. 6.9.17 Peripheral File Map
    10. 6.10 Input/Output Schematics
      1. 6.10.1  Port P1, P1.0 to P1.5, Input/Output With Schmitt Trigger
      2. 6.10.2  Port P1, P1.6, P1.7, Input/Output With Schmitt Trigger
      3. 6.10.3  Port P2, P2.0 to P2.3, P2.6 to P2.7, Input/Output With Schmitt Trigger
      4. 6.10.4  Port P2, P2.4 to P2.5, Input/Output With Schmitt Trigger
      5. 6.10.5  Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger
      6. 6.10.6  Port P3, P3.4 to P3.7, Input/Output With Schmitt Trigger
      7. 6.10.7  Port P4, P4.0 to P4.1, Input/Output With Schmitt Trigger
      8. 6.10.8  Port P4, P4.2 to P4.7, Input/Output With Schmitt Trigger
      9. 6.10.9  Port P5, P5.0, Input/Output With Schmitt Trigger
      10. 6.10.10 Port P5, P5.1, Input/Output With Schmitt Trigger
      11. 6.10.11 Port P5, P5.2 to P5.4, Input/Output With Schmitt Trigger
      12. 6.10.12 Port P5, P5.5 to P5.7, Input/Output With Schmitt Trigger
      13. 6.10.13 Port P6, P6.0, P6.2, and P6.4, Input/Output With Schmitt Trigger
      14. 6.10.14 Port P6, P6.1, P6.3, and P6.5 Input/Output With Schmitt Trigger
      15. 6.10.15 Port P6, P6.6, Input/Output With Schmitt Trigger
      16. 6.10.16 Port P6, P6.7, Input/Output With Schmitt Trigger
      17. 6.10.17 Port P7, P7.0 to P7.3, Input/Output With Schmitt Trigger
      18. 6.10.18 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
      19. 6.10.19 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
      20. 6.10.20 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
      21. 6.10.21 Port P10, P10.0 to P10.5, Input/Output With Schmitt Trigger
      22. 6.10.22 Port P10, P10.6, Input/Output With Schmitt Trigger
      23. 6.10.23 Port P10, P10.7, Input/Output With Schmitt Trigger
      24. 6.10.24 VeREF+/DAC0
      25. 6.10.25 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger or Output
      26. 6.10.26 JTAG Fuse Check Mode
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Getting Started and Next Steps
      2. 7.1.2 Development Tools Support
        1. 7.1.2.1 Hardware Features
        2. 7.1.2.2 Recommended Hardware Options
          1. 7.1.2.2.1 Target Socket Boards
          2. 7.1.2.2.2 Experimenter Boards
          3. 7.1.2.2.3 Debugging and Programming Tools
          4. 7.1.2.2.4 Production Programmers
        3. 7.1.2.3 Recommended Software Options
          1. 7.1.2.3.1 Integrated Development Environments
          2. 7.1.2.3.2 MSP430Ware
          3. 7.1.2.3.3 Command-Line Programmer
      3. 7.1.3 Device and Development Tool Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Related Links
    4. 7.4 Community Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Export Control Notice
    8. 7.8 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

1 Device Overview

1.1 Features

  • Low Supply-Voltage Range: 1.8 V to 3.6 V
  • Ultra-Low Power Consumption
    • Active Mode: 400 µA at 1 MHz, 2.2 V
    • Standby Mode: 1.3 µA
    • Off Mode (RAM Retention): 0.22 µA
  • Five Power-Saving Modes
  • Wakeup From Standby Mode in Less Than 6 µs
  • 16-Bit RISC Architecture, Extended Memory, 125‑ns Instruction Cycle Time
  • Three-Channel Internal DMA
  • 12-Bit Analog-to-Digital Converter (ADC) With Internal Reference, Sample-and-Hold and Autoscan Feature
  • Three Configurable Operational Amplifiers
  • Dual 12-Bit Digital-to-Analog Converters (DACs) With Synchronization
  • 16-Bit Timer_A With Three Capture/Compare Registers
  • 16-Bit Timer_B With Seven Capture/Compare-With-Shadow Registers
  • On-Chip Comparator
  • Supply Voltage Supervisor and Monitor With Programmable Level Detection
  • Serial Communication Interface (USART1), Select Asynchronous UART or Synchronous SPI by Software
  • Universal Serial Communication Interface
    • Enhanced UART Supports Automatic Baud-Rate Detection
    • IrDA Encoder and Decoder
    • Synchronous SPI
    • I2C
  • Serial Onboard Programming, Programmable Code Protection by Security Fuse
  • Brownout Detector
  • Basic Timer With Real-Time Clock (RTC) Feature
  • Integrated LCD Driver up to 160 Segments With Regulated Charge Pump
  • Section 3 Summarizes the Available Family Members
    • MSP430FG4616, MSP430FG4616
      92KB+256B of Flash or ROM
      4KB of RAM
    • MSP430FG4617, MSP430CG4617
      92KB+256B of Flash or ROM
      8KB of RAM
    • MSP430FG4618, MSP430CG4618
      116KB+256B of Flash or ROM
      8KB of RAM
    • MSP430FG4619, MSP430CG4619
      120KB+256B of Flash or ROM
      4KB of RAM
  • For Complete Module Descriptions, see the MSP430x4xx Family User’s Guide (SLAU056)

1.2 Applications

  • Portable Medical Applications
  • E-Meter Applications

1.3 Description

The TI MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to active mode in less than 6 µs.

The MSP430xG461x series are microcontroller configurations with two 16-bit timers, a high-performance 12-bit ADC, dual 12-bit DACs, three configurable operational amplifiers, one universal serial communication interface (USCI), one universal synchronous/asynchronous communication interface (USART), DMA, 80 I/O pins, and a segment liquid crystal display (LCD) driver with regulated charge pump.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE(2)
MSP430FG4619IPZ LQFP (100) 14 mm × 14 mm
MSP430FG4619IZQW MicroStar Junior™ BGA (113) 7 mm × 7 mm
(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 8, or see the TI website at www.ti.com.
(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 8.

1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram.

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_fbd.gifFigure 1-1 Functional Block Diagram