SLAS508J April   2006  – June 2015 MSP430FG4616 , MSP430FG4617 , MSP430FG4618 , MSP430FG4619

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3 Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Supply Current Into AVCC + DVCC Excluding External Current
    5. 5.5  Thermal Characteristics
    6. 5.6  Schmitt-Trigger Inputs - Ports P1 to P10, RST/NMI, JTAG (TCK, TMS, TDI/TCLK,TDO/TDI)
    7. 5.7  Inputs Px.x, TAx, TBX
    8. 5.8  Leakage Current - Ports P1 to P10
    9. 5.9  Outputs - Ports P1 to P10
    10. 5.10 Output Frequency
    11. 5.11 Typical Characteristics - Outputs
    12. 5.12 Wake-up Timing From LPM3
    13. 5.13 RAM
    14. 5.14 LCD_A
    15. 5.15 Comparator_A
    16. 5.16 Typical Characteristics - Comparator_A
    17. 5.17 POR, BOR
    18. 5.18 SVS (Supply Voltage Supervisor and Monitor)
    19. 5.19 DCO
    20. 5.20 Crystal Oscillator, LFXT1 Oscillator
    21. 5.21 Crystal Oscillator, XT2 Oscillator
    22. 5.22 USCI (UART Mode)
    23. 5.23 USCI (SPI Master Mode)
    24. 5.24 USCI (SPI Slave Mode)
    25. 5.25 USCI (I2C Mode)
    26. 5.26 USART1
    27. 5.27 12-Bit ADC, Power Supply and Input Range Conditions
    28. 5.28 12-Bit ADC, External Reference
    29. 5.29 12-Bit ADC, Built-In Reference
    30. 5.30 12-Bit ADC, Timing Parameters
    31. 5.31 12-Bit ADC, Linearity Parameters
    32. 5.32 12-Bit ADC, Temperature Sensor and Built-In VMID
    33. 5.33 12-Bit DAC, Supply Specifications
    34. 5.34 12-Bit DAC, Linearity Specifications
    35. 5.35 12-Bit DAC, Output Specifications
    36. 5.36 12-Bit DAC, Reference Input Specifications
    37. 5.37 12-Bit DAC, Dynamic Specifications
    38. 5.38 12-Bit DAC, Dynamic Specifications Continued
    39. 5.39 Operational Amplifier OA, Supply Specifications
    40. 5.40 Operational Amplifier OA, Input/Output Specifications
    41. 5.41 Operational Amplifier OA, Dynamic Specifications
    42. 5.42 Operational Amplifier OA, Typical Characteristics
    43. 5.43 Operational Amplifier OA Feedback Network, Noninverting Amplifier Mode (OAFCx = 4)
    44. 5.44 Operational Amplifier OA Feedback Network, Inverting Amplifier Mode (OAFCx = 6)
    45. 5.45 Flash Memory (FG461x Devices Only)
    46. 5.46 JTAG Interface
    47. 5.47 JTAG Fuse
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Special Function Registers (SFRs)
      1. 6.5.1 Interrupt Enable 1 and 2
      2. 6.5.2 Interrupt Flag Register 1 and 2
      3. 6.5.3 Module Enable Registers 1 and 2
    6. 6.6  Memory Organization
    7. 6.7  Bootstrap Loader (BSL)
    8. 6.8  Flash Memory
    9. 6.9  Peripherals
      1. 6.9.1  DMA Controller
      2. 6.9.2  Oscillator and System Clock
      3. 6.9.3  Brownout, Supply Voltage Supervisor (SVS)
      4. 6.9.4  Digital I/O
      5. 6.9.5  Basic Timer1 and Real-Time Clock
      6. 6.9.6  LCD_A Drive With Regulated Charge Pump
      7. 6.9.7  Watchdog Timer (WDT+)
      8. 6.9.8  Universal Serial Communication Interface (USCI)
      9. 6.9.9  USART1
      10. 6.9.10 Hardware Multiplier
      11. 6.9.11 Timer_A3
      12. 6.9.12 Timer_B7
      13. 6.9.13 Comparator_A
      14. 6.9.14 ADC12
      15. 6.9.15 DAC12
      16. 6.9.16 OA
      17. 6.9.17 Peripheral File Map
    10. 6.10 Input/Output Schematics
      1. 6.10.1  Port P1, P1.0 to P1.5, Input/Output With Schmitt Trigger
      2. 6.10.2  Port P1, P1.6, P1.7, Input/Output With Schmitt Trigger
      3. 6.10.3  Port P2, P2.0 to P2.3, P2.6 to P2.7, Input/Output With Schmitt Trigger
      4. 6.10.4  Port P2, P2.4 to P2.5, Input/Output With Schmitt Trigger
      5. 6.10.5  Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger
      6. 6.10.6  Port P3, P3.4 to P3.7, Input/Output With Schmitt Trigger
      7. 6.10.7  Port P4, P4.0 to P4.1, Input/Output With Schmitt Trigger
      8. 6.10.8  Port P4, P4.2 to P4.7, Input/Output With Schmitt Trigger
      9. 6.10.9  Port P5, P5.0, Input/Output With Schmitt Trigger
      10. 6.10.10 Port P5, P5.1, Input/Output With Schmitt Trigger
      11. 6.10.11 Port P5, P5.2 to P5.4, Input/Output With Schmitt Trigger
      12. 6.10.12 Port P5, P5.5 to P5.7, Input/Output With Schmitt Trigger
      13. 6.10.13 Port P6, P6.0, P6.2, and P6.4, Input/Output With Schmitt Trigger
      14. 6.10.14 Port P6, P6.1, P6.3, and P6.5 Input/Output With Schmitt Trigger
      15. 6.10.15 Port P6, P6.6, Input/Output With Schmitt Trigger
      16. 6.10.16 Port P6, P6.7, Input/Output With Schmitt Trigger
      17. 6.10.17 Port P7, P7.0 to P7.3, Input/Output With Schmitt Trigger
      18. 6.10.18 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
      19. 6.10.19 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
      20. 6.10.20 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
      21. 6.10.21 Port P10, P10.0 to P10.5, Input/Output With Schmitt Trigger
      22. 6.10.22 Port P10, P10.6, Input/Output With Schmitt Trigger
      23. 6.10.23 Port P10, P10.7, Input/Output With Schmitt Trigger
      24. 6.10.24 VeREF+/DAC0
      25. 6.10.25 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger or Output
      26. 6.10.26 JTAG Fuse Check Mode
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Getting Started and Next Steps
      2. 7.1.2 Development Tools Support
        1. 7.1.2.1 Hardware Features
        2. 7.1.2.2 Recommended Hardware Options
          1. 7.1.2.2.1 Target Socket Boards
          2. 7.1.2.2.2 Experimenter Boards
          3. 7.1.2.2.3 Debugging and Programming Tools
          4. 7.1.2.2.4 Production Programmers
        3. 7.1.2.3 Recommended Software Options
          1. 7.1.2.3.1 Integrated Development Environments
          2. 7.1.2.3.2 MSP430Ware
          3. 7.1.2.3.3 Command-Line Programmer
      3. 7.1.3 Device and Development Tool Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Related Links
    4. 7.4 Community Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Export Control Notice
    8. 7.8 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

6 Detailed Description

6.1 CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.

The MSP430xG461x device family uses the MSP430X CPU and is completely backwards compatible with the MSP430 CPU. For a complete description of the MSP430X CPU, refer to the MSP430x4xx Family User’s Guide (SLAU056).

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_RISCarch.gif

6.2 Instruction Set

The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data. Table 6-1 shows examples of the three types of instruction formats; the address modes are listed in Table 6-2.

Table 6-1 Instruction Word Formats

FORMAT EXAMPLE OPERATION
Dual operands, source-destination ADD R4,R5 R4 + R5 → R5
Single operands, destination only CALL R8 PC→ (TOS), R8 → PC
Relative jump, un/conditional JNE Jump-on-equal bit = 0

Table 6-2 Address Mode Descriptions

ADDRESS MODE S(1) D(1) SYNTAX EXAMPLE OPERATION
Register MOV Rs,Rd MOV R10,R11 R10 → R11
Indexed MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)→ M(6+R6)
Symbolic (PC relative) MOV EDE,TONI M(EDE) → M(TONI)
Absolute MOV & MEM, & TCDAT M(MEM) → M(TCDAT)
Indirect MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) → M(Tab+R6)
Indirect autoincrement MOV @Rn+,Rm MOV @R10+,R11 M(R10) → R11
R10 + 2→ R10
Immediate MOV #X,TONI MOV #45,TONI #45 → M(TONI)
(1) NOTE: S = source D = destination

6.3 Operating Modes

These devices have one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

  • Active mode (AM)
    • All clocks are active
  • Low-power mode 0 (LPM0)
    • CPU is disabled
    • ACLK and SMCLK remain active. MCLK is disabled
    • FLL+ loop control remains active
  • Low-power mode 1 (LPM1)
    • CPU is disabled
    • FLL+ loop control is disabled
    • ACLK and SMCLK remain active. MCLK is disabled
  • Low-power mode 2 (LPM2)
    • CPU is disabled
    • MCLK, FLL+ loop control and DCOCLK are disabled
    • DCO DC generator remains enabled
    • ACLK remains active
  • Low-power mode 3 (LPM3)
    • CPU is disabled
    • MCLK, FLL+ loop control, and DCOCLK are disabled
    • DCO DC generator is disabled
    • ACLK remains active
  • Low-power mode 4 (LPM4)
    • CPU is disabled
    • ACLK is disabled
    • MCLK, FLL+ loop control, and DCOCLK are disabled
    • DCO DC generator is disabled
    • Crystal oscillator is stopped

6.4 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 6-3 Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
WDTIFG
KEYV (1)(2)
Reset 0FFFEh 31, highest
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (1)(3)
OFIFG(1)(3)
ACCVIFG(1)(4)(2)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh 30
Timer_B7 TBCCR0 CCIFG0(4) Maskable 0FFFAh 29
Timer_B7 TBCCR1 CCIFG1 to TBCCR6 CCIFG6, TBIFG(1)(4) Maskable 0FFF8h 28
Comparator_A CAIFG Maskable 0FFF6h 27
Watchdog Timer+ WDTIFG Maskable 0FFF4h 26
USCI_A0, USCI_B0 Receive UCA0RXIFG, UCB0RXIFG(1) Maskable 0FFF2h 25
USCI_A0, USCI_B0 Transmit UCA0TXIFG, UCB0TXIFG (1) Maskable 0FFF0h 24
ADC12 ADC12IFG (1)(4) Maskable 0FFEEh 23
Timer_A3 TACCR0 CCIFG0(4) Maskable 0FFECh 22
Timer_A3 TACCR1 CCIFG1 and TACCR2 CCIFG2, TAIFG(1)(4) Maskable 0FFEAh 21
I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7(1)(4) Maskable 0FFE8h 20
USART1 Receive URXIFG1 Maskable 0FFE6h 19
USART1 Transmit UTXIFG1 Maskable 0FFE4h 18
I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7 (1)(4) Maskable 0FFE2h 17
Basic Timer 1, RTC BTIFG Maskable 0FFE0h 16
DMA DMA0IFG, DMA1IFG, DMA2IFG(1)(4) Maskable 0FFDEh 15
DAC12 DAC12.0IFG, DAC12.1IFG(1)(4) Maskable 0FFDCh 14
Reserved Reserved(5) 0FFDAh 13
0FFC0h 0, lowest
(1) Multiple source flags
(2) Access and key violations, KEYV and ACCVIFG, only applicable to FG devices.
(3) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh). (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(4) Interrupt flags are located in the module.
(5) The interrupt vectors at addresses 0FFDAh to 0FFC0h are not used in this device and can be used for regular program code if necessary.

6.5 Special Function Registers (SFRs)

The MSP430 SFRs are in the lowest address space and are organized as byte mode registers. SFRs should be accessed with byte instructions.

Legend
rw Bit can be read and written.
rw-0, rw-1 Bit can be read and written. It is Reset or Set by PUC.
rw-(0), rw-(1) Bit can be read and written. It is Reset or Set by POR.
MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_legend.gif SFR bit is not present in device

6.5.1 Interrupt Enable 1 and 2

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_enable1.gif
WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as a general-purpose timer.
OFIE Oscillator fault-interrupt enable
NMIIE Nonmaskable interrupt enable
ACCVIE Flash access violation interrupt enable
MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_enable2.gif
UCA0RXIE USCI_A0 receive-interrupt enable
UCA0TXIE USCI_A0 transmit-interrupt enable
UCB0RXIE USCI_B0 receive-interrupt enable
UCB0TXIE USCI_B0 transmit-interrupt enable
URXIE1 USART1 UART and SPI receive-interrupt enable
UTXIE1 USART1 UART and SPI transmit-interrupt enable
BTIE Basic timer interrupt enable

6.5.2 Interrupt Flag Register 1 and 2

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_flagreg1.gif
WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode
OFIFG Flag set on oscillator fault
NMIIFG Set by the RST/NMI pin
MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_flagreg2.gif
UCA0RXIFG USCI_A0 receive-interrupt flag
UCA0TXIFG USCI_A0 transmit-interrupt flag
UCB0RXIFG USCI_B0 receive-interrupt flag
UCB0TXIFG USCI_B0 transmit-interrupt flag
URXIFG0 USART1: UART and SPI receive flag
UTXIFG0 USART1: UART and SPI transmit flag
BTIFG Basic timer flag

6.5.3 Module Enable Registers 1 and 2

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_mod_en_reg1.gif
URXE1 USART1: UART mode receive enable
UTXE1 USART1: UART mode transmit enable
USPIE1 USART1: SPI mode transmit and receive enable
MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_mod_en_reg2.gif
URXE1 USART1: UART mode receive enable
UTXE1 USART1: UART mode transmit enable
USPIE1 USART1: SPI mode transmit and receive enable

6.6 Memory Organization

Table 6-4 summarizes the memory organization for the FG461x devices, and Table 6-5 summarizes the memory organization for the CG461x devices.

Table 6-4 MSP430FG461x Memory Organization

MSP430FG4616 MSP430FG4617 MSP430FG4618 MSP430FG4619
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
92KB
0FFFFh-0FFC0h
018FFFh-002100h
92KB
0FFFFh-0FFC0h
019FFFh-003100h
116KB
0FFFFh-0FFC0h
01FFFFh-003100h
120KB
0FFFFh-0FFC0h
01FFFFh-002100h
RAM Total Size 4KB
020FFh-01100h
8KB
030FFh-01100h
8KB
030FFh-01100h
4KB
020FFh-01100h
Extended Size 2KB
020FFh-01900h
6KB
030FFh-01900h
6KB
030FFh-01900h
2KB
020FFh-01900h
Mirrored Size 2KB
018FFh-01100h
2KB
018FFh-01100h
2KB
018FFh-01100h
2KB
018FFh-01100h
Information memory Size
Flash
256 Byte
010FFh-01000h
256 Byte
010FFh-01000h
256 Byte
010FFh-01000h
256 Byte
010FFh-01000h
Boot memory Size
ROM
1KB
0FFFh-0C00h
1KB
0FFFh-0C00h
1KB
0FFFh-0C00h
1KB
0FFFh-0C00h
RAM
(Mirrored at 018FFh-01100h)
Size 2KB
09FFh-0200h
2KB
09FFh-0200h
2KB
09FFh-0200h
2KB
09FFh-0200h
Peripherals 16 bit
8 bit
8-bit SFR
01FFh-0100h
0FFh-010h
0Fh-00h
01FFh-0100h
0FFh-010h
0Fh-00h
01FFh-0100h
0FFh-010h
0Fh-00h
01FFh-0100h
0FFh-010h
0Fh-00h

Table 6-5 MSP430CG461x Memory Organization

MSP430CG4616 MSP430CG4617 MSP430CG4618 MSP430CG4619
Memory
Main: interrupt vector
Main: code memory
Size
ROM
ROM
92KB
0FFFFh-0FFC0h
018FFFh-002100h
92KB
0FFFFh-0FFC0h
019FFFh-003100h
116KB
0FFFFh-0FFC0h
01FFFFh-003100h
120KB
0FFFFh-0FFC0h
01FFFFh-002100h
RAM Total Size 4KB
020FFh-01100h
8KB
030FFh-01100h
8KB
030FFh-01100h
4KB
020FFh-01100h
Extended Size 2KB
020FFh-01900h
6KB
030FFh-01900h
6KB
030FFh-01900h
2KB
020FFh-01900h
Mirrored Size 2KB
018FFh-01100h
2KB
018FFh-01100h
2KB
018FFh-01100h
2KB
018FFh-01100h
Information memory Size
ROM
256 Byte
010FFh-01000h
256 Byte
010FFh-01000h
256 Byte
010FFh-01000h
256 Byte
010FFh-01000h
Boot memory
(Optional on CG)
Size
ROM
1KB
0FFFh-0C00h
1KB
0FFFh-0C00h
1KB
0FFFh-0C00h
1KB
0FFFh-0C00h
RAM
(Mirrored at 018FFh-01100h)
Size 2KB
09FFh-0200h
2KB
09FFh-0200h
2KB
09FFh-0200h
2KB
09FFh-0200h
Peripherals 16 bit
8 bit
8-bit SFR
01FFh-0100h
0FFh-010h
0Fh-00h
01FFh-0100h
0FFh-010h
0Fh-00h
01FFh-0100h
0FFh-010h
0Fh-00h
01FFh-0100h
0FFh-010h
0Fh-00h

6.7 Bootstrap Loader (BSL)

The BSL lets users program the flash memory or RAM using a UART serial interface. Access to the MCU memory through the BSL is protected by user-defined password. A bootstrap loader security key is provided at address 0FFBEh to disable the BSL completely or to disable the erasure of the flash if an invalid password is supplied. The BSL is optional for ROM-based devices. For complete description of the features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap Loader (SLAA089).

BSLKEY DESCRIPTION
00000h Erasure of flash disabled if an invalid password is supplied
0AA55h BSL disabled
any other value BSL enabled
BSL FUNCTION PZ/ZQW PACKAGE PINS
Data Transmit 87/A7 – P1.0
Data Receiver 86/E7 – P1.1

6.8 Flash Memory

The flash memory can be programmed by the JTAG port, the bootstrap loader, or in system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

  • Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size.
  • Segments 0 to n may be erased in one step, or each segment may be individually erased.
  • Segments A and B can be erased individually, or as a group with segments 0-n. Segments A and B are also called information memory.
  • New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory before the first use.

6.9 Peripherals

Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be handled using all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide.

6.9.1 DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or from a peripheral.

6.9.2 Oscillator and System Clock

The clock system in the MSP430xG461x family of devices is supported by the FLL+ module, which includes support for a 32768-Hz watch crystal oscillator, an internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and low power consumption. The FLL+ features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turnon clock source and stabilizes in less than 6 µs. The FLL+ module provides the following clock signals:

  • Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal
  • Main clock (MCLK), the system clock used by the CPU
  • Submain clock (SMCLK), the subsystem clock used by the peripheral modules
  • ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8

6.9.3 Brownout, Supply Voltage Supervisor (SVS)

The brownout circuit provides the proper internal reset signal to the device during power-on and power-off. The SVS circuitry detects if the supply voltage drops below a user-selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not automatically reset).

The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not have ramped to VCC(min) at that time. The user must make sure the default FLL+ settings are not changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).

6.9.4 Digital I/O

There are ten 8-bit I/O ports implemented—ports P1 through P10:

  • All individual I/O bits are independently programmable.
  • Any combination of input, output, and interrupt conditions is possible.
  • Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
  • Read and write access to port-control registers is supported by all instructions
  • Ports P7/P8 and P9/P10 can be accessed word-wise as ports PA and PB, respectively.

6.9.5 Basic Timer1 and Real-Time Clock

The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Basic Timer1 is extended to provide an integrated real-time clock (RTC). An internal calendar compensates for months with less than 31 days and includes leap-year correction.

6.9.6 LCD_A Drive With Regulated Charge Pump

The LCD_A driver generates the segment and common signals required to drive a segment LCD display. The LCD_A controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral. The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump. Furthermore it is possible to control the level of the LCD voltage and, thus, contrast by software.

6.9.7 Watchdog Timer (WDT+)

The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.

6.9.8 Universal Serial Communication Interface (USCI)

The USCI modules are used for serial data communication. The USCI module supports synchronous communication protocols like SPI (3-pin or 4-pin), I2C, and asynchronous communication protocols like UART, enhanced UART with automatic baudrate detection, and IrDA.

The USCI_A0 module provides support for SPI (3-pin or 4-pin), UART, enhanced UART and IrDA.

The USCI_B0 module provides support for SPI (3-pin or 4-pin) and I2C.

6.9.9 USART1

The hardware universal synchronous/asynchronous receive transmit (USART) peripheral module is used for serial data communication. The USART supports synchronous SPI (3-pin or 4-pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.

6.9.10 Hardware Multiplier

The multiplication operation is supported by a dedicated peripheral module. The module performs 16×16, 16×8, 8×16, and 8×8 bit operations. The module supports signed and unsigned multiplication as well as signed and unsigned multiply-and-accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required.

6.9.11 Timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 6-6 Timer_A3 Signal Connections

INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUT SIGNAL OUTPUT PIN NUMBER
PZ/ZQW PZ/ZQW
82/B9 - P1.5 TACLK TACLK Timer NA
ACLK ACLK
SMCLK SMCLK
82/B9 - P1.5 TACLK INCLK
87/A7 - P1.0 TA0 CCI0A CCR0 TA0 87/A7 - P1.0
86/E7 - P1.1 TA0 CCI0B
DVSS GND
DVCC VCC
85/D7 - P1.2 TA1 CCI1A CCR1 TA1 85/D7 - P1.2
CAOUT (internal) CCI1B ADC12 (internal)
DVSS GND
DVCC VCC
79/A10 - P2.0 TA2 CCI2A CCR2 TA2 79/A10 - P2.0
ACLK (internal) CCI2B
DVSS GND
DVCC VCC

6.9.12 Timer_B7

Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 6-7 Timer_B7 Signal Connections

INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUT SIGNAL OUTPUT PIN NUMBER
PZ/ZQW PZ/ZQW
83/B8 - P1.4 TBCLK TBCLK Timer NA
ACLK ACLK
SMCLK SMCLK
83/B8 - P1.4 TBCLK INCLK
78/D8 - P2.1 TB0 CCI0A CCR0CCR0 TB0TB0 78/D8 - P2.1
78/D8 - P2.1 TB0 CCI0B ADC12 (internal)
DVSS GND
DVCC VCC
77/E8 - P2.2 TB1 CCI1A CCR1 TB1 77/E8 - P2.2
77/E8 - P2.2 TB1 CCI1B ADC12 (internal)
DVSS GND
DVCC VCC
76/A11 - P2.3 TB2 CCI2A CCR2 TB2 76/A11 - P2.3
76/A11 - P2.3 TB2 CCI2B
DVSS GND
DVCC VCC
67/E12 - P3.4 TB3 CCI3A CCR3 TB3 67/E12 - P3.4
67/E12 - P3.4 TB3 CCI3B
DVSS GND
DVCC VCC
66/G9 - P3.5 TB4 CCI4A CCR4 TB4 66/G9 - P3.5
66/G9 - P3.5 TB4 CCI4B
DVSS GND
DVCC VCC
65/F11 - P3.6 TB5 CCI5A CCR5 TB5 65/F11 - P3.6
65/F11 - P3.6 TB5 CCI5B
DVSS GND
DVCC VCC
64/F12 - P3.7 TB6 CCI6A CCR6 TB6 64/F12 - P3.7
ACLK (internal) CCI6B
DVSS GND
DVCC VCC

6.9.13 Comparator_A

The primary function of the comparator_A module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals.

6.9.14 ADC12

The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention.

6.9.15 DAC12

The DAC12 module is a 12-bit R-ladder voltage-output DAC. The DAC12 can be used in 8-bit or 12-bit mode and can be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may be grouped together for synchronous operation.

6.9.16 OA

The MSP430xG461x has three configurable low-current general-purpose operational amplifiers. Each OA input and output terminal is software-selectable and offer a flexible choice of connections for various applications. The OA op amps primarily support front-end analog signal conditioning before analog-to-digital conversion.

Table 6-8 OA Signal Connections

INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL OUTPUT PIN NUMBER
PZ PZ
95 - P6.0 OA0I0 OA0I0 OA0 OA0OUT OA0O 96 - P6.1
97 - P6.2 OA0I1 OA0I1 OA0O ADC12 (internal)
DAC12_0OUT
(internal)
DAC12_0OUT
DAC12_1OUT
(internal)
DAC12_1OUT
3- P6.4 OA1I0 OA1I0 OA1 OA1OUT OA1O 2- P6.3
13 - P5.0 OA1I1 OA1I1 OA1O 13- P5.0
DAC12_0OUT
(internal)
DAC12_0OUT OA1O ADC12 (internal)
DAC12_1OUT
(internal)
DAC12_1OUT
5- P6.6 OA2I0 OA2I0 OA2 OA2OUT OA2O 4- P6.5
14 - P10.7 OA2I1 OA2I1 OA2O 14 - P10.7
DAC12_0OUT
(internal)
DAC12_0OUT OA2O ADC12 (internal)
DAC12_1OUT
(internal)
DAC12_1OUT

6.9.17 Peripheral File Map

Table 6-9 lists the registers and addresses for peripherals with word access. Table 6-10 lists the registers and addresses for peripherals with byte access.

Table 6-9 Peripherals With Word Access

MODULE REGISTER NAME ACRONYM ADDRESS
Watchdog+ Watchdog timer control WDTCTL 0120h
Timer_B7 Capture/compare register 6
Capture/compare register 5
Capture/compare register 4
Capture/compare register 3
Capture/compare register 2
Capture/compare register 1
Capture/compare register 0
Timer_B register
Capture/compare control 6
Capture/compare control 5
Capture/compare control 4
Capture/compare control 3
Capture/compare control 2
Capture/compare control 1
Capture/compare control 0
Timer_B control
Timer_B interrupt vector
TBCCR6
TBCCR5
TBCCR4
TBCCR3
TBCCR2
TBCCR1
TBCCR0
TBR
TBCCTL6
TBCCTL5
TBCCTL4
TBCCTL3
TBCCTL2
TBCCTL1
TBCCTL0
TBCTL
TBIV
019Eh
019Ch
019Ah
0198h
0196h
0194h
0192h
0190h
018Eh
018Ch
018Ah
0188h
0186h
0184h
0182h
0180h
011Eh
Timer_A3 Capture/compare register 2
Capture/compare register 1
Capture/compare register 0
Timer_A register
Capture/compare control 2
Capture/compare control 1
Capture/compare control 0
Timer_A control
Timer_A interrupt vector
TACCR2
TACCR1
TACCR0
TAR
TACCTL2
TACCTL1
TACCTL0
TACTL
TAIV
0176h
0174h
0172h
0170h
0166h
0164h
0162h
0160h
012Eh
Hardware Multiplier Sum extend
Result high word
Result low word
Second operand
Multiply signed + accumulate/operand1
Multiply + accumulate/operand1
Multiply signed/operand1
Multiply unsigned/operand1
SUMEXT
RESHI
RESLO
OP2
MACS
MAC
MPYS
MPY
013Eh
013Ch
013Ah
0138h
0136h
0134h
0132h
0130h
Flash
(FG devices only)
Flash control 3
Flash control 2
Flash control 1
FCTL3
FCTL2
FCTL1
012Ch
012Ah
0128h
DMA DMA module control 0
DMA module control 1
DMA interrupt vector
DMACTL0
DMACTL1
DMAIV
0122h
0124h
0126h
DMA Channel 0 DMA channel 0 control
DMA channel 0 source address
DMA channel 0 destination address
DMA channel 0 transfer size
DMA0CTL
DMA0SA
DMA0DA
DMA0SZ
01D0h
01D2h
01D6h
01DAh
DMA Channel 1 DMA channel 1 control
DMA channel 1 source address
DMA channel 1 destination address
DMA channel 1 transfer size
DMA1CTL
DMA1SA
DMA1DA
DMA1SZ
01DCh
01DEh
01E2h
01E6h
DMA Channel 2 DMA channel 2 control
DMA channel 2 source address
DMA channel 2 destination address
DMA channel 2 transfer size
DMA2CTL
DMA2SA
DMA2DA
DMA2SZ
01E8h
01EAh
01EEh
01F2h
ADC12
See also Table 6-10
Conversion memory 15
Conversion memory 14
Conversion memory 13
Conversion memory 12
Conversion memory 11
Conversion memory 10
Conversion memory 9
Conversion memory 8
Conversion memory 7
Conversion memory 6
Conversion memory 5
Conversion memory 4
Conversion memory 3
Conversion memory 2
Conversion memory 1
Conversion memory 0
Interrupt-vector-word register
Inerrupt-enable register
Inerrupt-flag register
Control register 1
Control register 0
ADC12MEM15
ADC12MEM14
ADC12MEM13
ADC12MEM12
ADC12MEM11
ADC12MEM10
ADC12MEM9
ADC12MEM8
ADC12MEM7
ADC12MEM6
ADC12MEM5
ADC12MEM4
ADC12MEM3
ADC12MEM2
ADC12MEM1
ADC12MEM0
ADC12IV
ADC12IE
ADC12IFG
ADC12CTL1
ADC12CTL0
015Eh
015Ch
015Ah
0158h
0156h
0154h
0152h
0150h
014Eh
014Ch
014Ah
0148h
0146h
0144h
0142h
0140h
01A8h
01A6h
01A4h
01A2h
01A0h
DAC12 DAC12_1 data
DAC12_1 control
DAC12_0 data
DAC12_0 control
DAC12_1DAT
DAC12_1CTL
DAC12_0DAT
DAC12_0CTL
01CAh
01C2h
01C8h
01C0h
Port PA Port PA selection
Port PA direction
Port PA output
Port PA input
PASEL
PADIR
PAOUT
PAIN
03Eh
03Ch
03Ah
038h
Port PB Port PB selection
Port PB direction
Port PB output
Port PB input
PBSEL
PBDIR
PBOUT
PBIN
00Eh
00Ch
00Ah
008h

Table 6-10 Peripherals With Byte Access

MODULE REGISTER NAME ACRONYM ADDRESS
OA2 Operational Amplifier 2 control register 1
Operational Amplifier 2 control register 0
OA2CTL1
OA2CTL0
0C5h
0C4h
OA1 Operational Amplifier 1 control register 1
Operational Amplifier 1 control register 0
OA1CTL1
OA1CTL0
0C3h
0C2h
OA0 Operational Amplifier 0 control register 1
Operational Amplifier 0 control register 0
OA0CTL1
OA0CTL0
0C1h
0C0h
LCD_A LCD Voltage Control 1
LCD Voltage Control 0
LCD Voltage Port Control 1
LCD Voltage Port Control 0
LCD memory 20
:
LCD memory 16
LCD memory 15
:
LCD memory 1
LCD control and mode
LCDAVCTL1
LCDAVCTL0
LCDAPCTL1
LCDAPCTL0
LCDM20
:
LCDM16
LCDM15
:
LCDM1
LCDCTL
0AFh
0AEh
0ADh
0ACh
0A4h
:
0A0h
09Fh
:
091h
090h
ADC12
(Memory control registers require byte access)
ADC memory-control register 15
ADC memory-control register 14
ADC memory-control register 13
ADC memory-control register 12
ADC memory-control register 11
ADC memory-control register 10
ADC memory-control register 9
ADC memory-control register 8
ADC memory-control register 7
ADC memory-control register 6
ADC memory-control register 5
ADC memory-control register 4
ADC memory-control register 3
ADC memory-control register 2
ADC memory-control register 1
ADC memory-control register 0
ADC12MCTL15
ADC12MCTL14
ADC12MCTL13
ADC12MCTL12
ADC12MCTL11
ADC12MCTL10
ADC12MCTL9
ADC12MCTL8
ADC12MCTL7
ADC12MCTL6
ADC12MCTL5
ADC12MCTL4
ADC12MCTL3
ADC12MCTL2
ADC12MCTL1
ADC12MCTL0
08Fh
08Eh
08Dh
08Ch
08Bh
08Ah
089h
088h
087h
086h
085h
084h
083h
082h
081h
080h
USART1 Transmit buffer
Receive buffer
Baud rate
Baud rate
Modulation control
Receive control
Transmit control
USART control
U1TXBUF
U1RXBUF
U1BR1
U1BR0
U1MCTL
U1RCTL
U1TCTL
U1CTL
07Fh
07Eh
07Dh
07Ch
07Bh
07Ah
079h
078h
USCI USCI I2C Slave Address
USCI I2C Own Address
USCI Synchronous Transmit Buffer
USCI Synchronous Receive Buffer
USCI Synchronous Status
USCI I2C Interrupt Enable
USCI Synchronous Bit Rate 1
USCI Synchronous Bit Rate 0
USCI Synchronous Control 1
USCI Synchronous Control 0
USCI Transmit Buffer
USCI Receive Buffer
USCI Status
USCI Modulation Control
USCI Baud Rate 1
USCI Baud Rate 0
USCI Control 1
USCI Control 0
USCI IrDA Receive Control
USCI IrDA Transmit Control
USCI LIN Control
UCBI2CSA
UCBI2COA
UCBTXBUF
UCBRXBUF
UCBSTAT
UCBI2CIE
UCBBR1
UCBBR0
UCBCTL1
UCBCTL0
UCATXBUF
UCARXBUF
UCASTAT
UCAMCTL
UCABR1
UCABR0
UCACTL1
UCACTL0
UCAIRRCTL
UCAIRTCTL
UCAABCTL
011Ah
0118h
06Fh
06Eh
06Dh
06Ch
06Bh
06Ah
069h
068h
067h
066h
065h
064h
063h
062h
061h
060h
05Fh
05Eh
05Dh
Comparator_A Comparator_A port disable
Comparator_A control 2
Comparator_A control 1
CAPD
CACTL2
CACTL1
05Bh
05Ah
059h
BrownOUT, SVS SVS control register (Reset by brownout signal) SVSCTL 056h
FLL+Clock FLL+ Control 1
FLL+ Control 0
System clock frequency control
System clock frequency integrator
System clock frequency integrator
FLL_CTL1
FLL_CTL0
SCFQCTL
SCFI1
SCFI0
054h
053h
052h
051h
050h
RTC
(Basic Timer 1)
Real Time Clock Year High Byte
Real Time Clock Year Low Byte
Real Time Clock Month
Real Time Clock Day of Month
Basic Timer1 Counter 2
Basic Timer1 Counter 1
Real Time Counter 4
(Real Time Clock Day of Week)
Real Time Counter 3
(Real Time Clock Hour)
Real Time Counter 2
(Real Time Clock Minute)
Real Time Counter 1
(Real Time Clock Second)
Real Time Clock Control
Basic Timer1 Control
RTCYEARH
RTCYEARL
RTCMON
RTCDAY
BTCNT2
BTCNT1
RTCNT4
(RTCDOW)
RTCNT3
(RTCHOUR)
RTCNT2
(RTCMIN)
RTCNT1
(RTCSEC)
RTCCTL
BTCTL
04Fh
04Eh
04Dh
04Ch
047h
046h
045h


044h


043h


042h


041h
040h
Port P10 Port P10 selection
Port P10 direction
Port P10 output
Port P10 input
P10SEL
P10DIR
P10OUT
P10IN
00Fh
00Dh
00Bh
009h
Port P9 Port P9 selection
Port P9 direction
Port P9 output
Port P9 input
P9SEL
P9DIR
P9OUT
P9IN
00Eh
00Ch
00Ah
008h
Port P8 Port P8 selection
Port P8 direction
Port P8 output
Port P8 input
P8SEL
P8DIR
P8OUT
P8IN
03Fh
03Dh
03Bh
039h
Port P7 Port P7 selection
Port P7 direction
Port P7 output
Port P7 input
P7SEL
P7DIR
P7OUT
P7IN
03Eh
03Ch
03Ah
038h
Port P6 Port P6 selection
Port P6 direction
Port P6 output
Port P6 input
P6SEL
P6DIR
P6OUT
P6IN
037h
036h
035h
034h
Port P5 Port P5 selection
Port P5 direction
Port P5 output
Port P5 input
P5SEL
P5DIR
P5OUT
P5IN
033h
032h
031h
030h
Port P4 Port P4 selection
Port P4 direction
Port P4 output
Port P4 input
P4SEL
P4DIR
P4OUT
P4IN
01Fh
01Eh
01Dh
01Ch
Port P3 Port P3 selection
Port P3 direction
Port P3 output
Port P3 input
P3SEL
P3DIR
P3OUT
P3IN
01Bh
01Ah
019h
018h
Port P2 Port P2 selection
Port P2 interrupt enable
Port P2 interrupt-edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
Port P2 input
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Port P1 Port P1 selection
Port P1 interrupt enable
Port P1 interrupt-edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
Port P1 input
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
026h
025h
024h
023h
022h
021h
020h
Special functions SFR module enable 2
SFR module enable 1
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
ME2
ME1
IFG2
IFG1
IE2
IE1
005h
004h
003h
002h
001h
000h

6.10 Input/Output Schematics

6.10.1 Port P1, P1.0 to P1.5, Input/Output With Schmitt Trigger

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_app1.gif

Table 6-11 Port P1 (P1.0 to P1.5) Pin Functions

PIN NAME (P1.x) x FUNCTION CONTROL BITS OR SIGNALS
P1DIR.x P1SEL.x
P1.0/TA0 0 P1.0 (I/O) I: 0; O: 1 0
Timer_A3.CCI0A 0 1
Timer_A3.TA0 1 1
P1.1/TA0/MCLK 1 P1.1 (I/O) I: 0; O: 1 0
Timer_A3.CCI0B 0 1
MCLK 1 1
P1.2/TA1 2 P1.2 (I/O) I: 0; O: 1 0
Timer_A3.CCI1A 0 1
Timer_A3.TA1 1 1
P1.3/TBOUTH/SVSOUT 3 P1.3 (I/O) I: 0; O: 1 0
Timer_B7.TBOUTH 0 1
SVSOUT 1 1
P1.4/TBCLK/SMCLK 4 P1.4 (I/O) I: 0; O: 1 0
Timer_B7.TBCLK 0 1
SMCLK 1 1
P1.5/TACLK/ACLK 5 P1.5 (I/O) I: 0; O: 1 0
Timer_A3.TACLK 0 1
ACLK 1 1

6.10.2 Port P1, P1.6, P1.7, Input/Output With Schmitt Trigger

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_app2.gif

Table 6-12 Port P1 (P1.6 and P1.7) Pin Functions

PIN NAME (P1.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
CAPD.x P1DIR.x P1SEL.x
P1.6/CA0 6 P1.6 (I/O) 0 I: 0; O: 1 0
CA0 1 X X
P1.7/CA1 7 P1.7 (I/O) 0 I: 0; O: 1 0
CA1 1 X X
(1) X = don't care

6.10.3 Port P2, P2.0 to P2.3, P2.6 to P2.7, Input/Output With Schmitt Trigger

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_app3.gif

Table 6-13 Port P2 (P2.0, P2.1, P2.2, P2.3, P2.6 and P2.7) Pin Functions

PIN NAME (P2.x) x FUNCTION CONTROL BITS OR SIGNALS
P2DIR.x P2SEL.x
P2.0/TA2 0 P2.0 (I/O) I: 0; O: 1 0
Timer_A3.CCI2A 0 1
Timer_A3.TA2 1 1
P2.1/TB0 1 P2.1 (I/O) I: 0; O: 1 0
Timer_B7.CCI0A and Timer_B7.CCI0B 0 1
Timer_B7.TB0(1) 1 1
P2.2/TB1 2 P2.2 (I/O) I: 0; O: 1 0
Timer_B7.CCI1A and Timer_B7.CCI1B 0 1
Timer_B7.TB1(1) 1 1
P2.3/TB3 3 P2.3 (I/O) I: 0; O: 1 0
Timer_B7.CCI2A and Timer_B7.CCI2B 0 1
Timer_B7.TB3(1) 1 1
P2.6/CAOUT 6 P2.6 (I/O) I: 0; O: 1 0
CAOUT 1 1
P2.7/ADC12CLK/DMAE0 7 P2.7 (I/O) I: 0; O: 1 0
ADC12CLK 1 1
DMAE0 0 1
(1) Setting TBOUTH causes all Timer_B outputs to be set to high impedance.

6.10.4 Port P2, P2.4 to P2.5, Input/Output With Schmitt Trigger

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_app4.gif

Table 6-14 Port P2 (P2.4 and P2.5) Pin Functions

PIN NAME (P2.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P2DIR.x P2SEL.x
P2.4/UCA0TXD 4 P2.4 (I/O) I: 0; O: 1 0
USCI_A0.UCA0TXD (2) X 1
P2.5/UCA0RXD 5 P2.5 (I/O) I: 0; O: 1 0
USCI_A0.UCA0RXD (2) X 1
(1) X = don't care
(2) When in USCI mode, P2.4 is set to output, P2.5 is set to input.

6.10.5 Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_app5.gif

Table 6-15 Port P3 (P3.0 to P3.3) Pin Functions

PIN NAME (P3.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P3DIR.x P3SEL.x
P3.0/UCB0STE 0 P3.0 (I/O) I: 0; O: 1 0
UCB0STE (2) X 1
P3.1/UCB0SIMO/UCB0SDA 1 P3.1 (I/O) I: 0; O: 1 0
UCB0SIMO/UCB0SDA (2)(3) X 1
P3.2/UCB0SOMI/UCB0SCL 2 P3.2 (I/O) I: 0; O: 1 0
UCB0SOMI/UCB0SCL (2)(3) X 1
P3.3/UCB0CLK 3 P3.3 (I/O) I: 0; O: 1 0
UCB0CLK (2) X 1
(1) X = don't care
(2) The pin direction is controlled by the USCI module.
(3) If the I2C functionality is selected the output drives only the logical 0 to VSS level.

6.10.6 Port P3, P3.4 to P3.7, Input/Output With Schmitt Trigger

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_app6.gif

Table 6-16 Port P3 (P3.4 to P3.7) Pin Functions

PIN NAME (P3.x) x FUNCTION CONTROL BITS OR SIGNALS
P3DIR.x P3SEL.x
P3.4/TB3 4 P3.4 (I/O) I: 0; O: 1 0
Timer_B7.CCI3A and Timer_B7.CCI3B 0 1
Timer_B7.TB3(1) 1 1
P3.5/TB4 5 P3.5 (I/O) I: 0; O: 1 0
Timer_B7.CCI4A and Timer_B7.CCI4B 0 1
Timer_B7.TB4 (1) 1 1
P3.6/TB5 6 P3.6 (I/O) I: 0; O: 1 0
Timer_B7.CCI5A and Timer_B7.CCI5B 0 1
Timer_B7.TB5(1) 1 1
P3.7/TB6 7 P3.7 (I/O) I: 0; O: 1 0
Timer_B7.CCI6A and Timer_B7.CCI6B 0 1
Timer_B7.TB6(1) 1 1
(1) Setting TBOUTH causes all Timer_B outputs to be set to high impedance.

6.10.7 Port P4, P4.0 to P4.1, Input/Output With Schmitt Trigger

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_app7.gif

Table 6-17 Port P4 (P4.0 to P4.1) Pin Functions

PIN NAME (P4.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P4DIR.x P4SEL.x
P4.0/UTXD1 0 P4.0 (I/O) I: 0; O: 1 0
USART1.UTXD1 (2) X 1
P4.1/URXD1 1 P4.1 (I/O) I: 0; O: 1 0
USART1.URXD1 (2) X 1
(1) X = don't care
(2) When in USART1 mode, P4.0 is set to output, P4.1 is set to input.

6.10.8 Port P4, P4.2 to P4.7, Input/Output With Schmitt Trigger

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_app8.gif

Table 6-18 Port P4 (P4.2 to P4.5) Pin Functions

PIN NAME (P4.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P4DIR.x P4SEL.x LCDS36
P4.2/STE1/S39 2 P4.2 (I/O) I: 0; O: 1 0 0
USART1.STE1 X 1 0
S39 X X 1
P4.3/SIMO/S38 3 P4.3 (I/O) I: 0; O: 1 0 0
USART1.SIMO1 (2) X 1 0
S38 X X 1
P4.4/SOMI/S37 4 P4.4 (I/O) I: 0; O: 1 0 0
USART1.SOMI1 (2) X 1 0
S37 X X 1
P4.5/SOMI/S36 5 P4.5 (I/O) I: 0; O: 1 0 0
USART1.UCLK1 (2) X 1 0
S36 X X 1
(1) X = don't care
(2) The pin direction is controlled by the USART1 module.

Table 6-19 Port P4 (P4.6 and P4.7) Pin Functions

PIN NAME (P4.x) x FUNCTION CONTROL BITS OR SIGNALS(2)
P4DIR.x P4SEL.x LCDS32
P4.6/UCA0TXD/S35 6 P4.6 (I/O) I: 0; O: 1 0 0
USCI_A0.UCA0TXD (1) X 1 0
S35 X X 1
P4.7/UCA0RXD/S34 7 P4.7 (I/O) I: 0; O: 1 0 0
USCI_A0.UCA0RXD (1) X 1 0
S34 X X 1
(1) When in USCI mode, P4.6 is set to output, P4.7 is set to input.
(2) X = don't care

6.10.9 Port P5, P5.0, Input/Output With Schmitt Trigger

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_app9.gif

Table 6-20 Port P5 (P5.0) Pin Functions

PIN NAME (P5.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P5DIR.x P5SEL.x INCHx OAPx (OA1)
OANx (OA1)
LCDS0
P5.0/S1/A13/OA1I1 0 P5.0 (I/O) I: 0; O: 1 0 X X 0
OAI11 0 X X 1 0
A13 (2) X 1 13 X X
S1 enabled X 0 X X 1
S1 disabled X 1 X X 1
(1) X = don't care
(2) Setting the P5SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.

6.10.10 Port P5, P5.1, Input/Output With Schmitt Trigger

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_app10.gif

Table 6-21 Port P5 (P5.1) Pin Functions

PIN NAME (P5.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P5DIR.x P5SEL.x INCHx DAC12.1OPS DAC12.1AMPx LCDS0
P5.1/S0/A12/DAC1 1 P5.1 (I/O) I: 0; O: 1 0 X 0 X 0
DAC1 high impedance X X X 1 0 X
DVSS X X X 1 1 X
DAC1 output X X X 1 >1 X
A12 (2) X 1 12 0 X 0
S0 enabled X 0 X 0 X 1
S0 disabled X 1 X 0 X 1
(1) X = don't care
(2) Setting the P5SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.

6.10.11 Port P5, P5.2 to P5.4, Input/Output With Schmitt Trigger

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_app11.gif

Table 6-22 Port P5 (P5.2 to P5.4) Pin Functions

PIN NAME (P5.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P5DIR.x P5SEL.x
P5.2/COM1 2 P5.2 (I/O) I: 0; O: 1 0
COM1 X 1
P5.3/COM2 3 P5.3 (I/O) I: 0; O: 1 0
COM2 X 1
P5.4/COM3 4 P5.4 (I/O) I: 0; O: 1 0
COM3 X 1
(1) X = don't care

6.10.12 Port P5, P5.5 to P5.7, Input/Output With Schmitt Trigger

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_app12.gif

Table 6-23 Port P5 (P5.5 to P5.7) Pin Functions

PIN NAME (P5.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P5DIR.x P5SEL.x
P5.5/R03 5 P5.5 (I/O) I: 0; O: 1 0
R03 X 1
P5.6/LCDREF/R13 6 P5.6 (I/O) I: 0; O: 1 0
R13 or LCDREF (2) X 1
P5.7/R03 7 P5.7 (I/O) I: 0; O: 1 0
R03 X 1
(1) X = don't care
(2) External reference for the LCD_A charge pump is applied when VLCDREFx = 01. Otherwise R13 is selected.

6.10.13 Port P6, P6.0, P6.2, and P6.4, Input/Output With Schmitt Trigger

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_app13.gif

Table 6-24 Port P6 (P6.0, P6.2, and P6.4) Pin Functions

PIN NAME (P6.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P6DIR.x P6SEL.x OAPx (OA0)
OANx (OA0)
OAPx (OA1)
OANx (OA1)
INCHx
P6.0/A0/OA0I0 0 P6.0 (I/O) I: 0; O: 1 0 X X X
OA0I0 0 X 0 X X
A0 (2) X 1 X X 0
P6.2/A2/OA0I1 2 P6.2 (I/O) I: 0; O: 1 0 X X X
OA0I1 0 X 1 X X
A2 (2) X 1 X X 2
P6.4/A4/OA1I0 4 P6.4 (I/O) I: 0; O: 1 0 X X X
OA1I0 0 X X 0 X
A4 (2) X 1 X X 4
(1) X = don't care
(2) Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.

6.10.14 Port P6, P6.1, P6.3, and P6.5 Input/Output With Schmitt Trigger

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_app14.gif

Table 6-25 Port P6 (P6.1, P6.3, and P6.5) Pin Functions

PIN NAME (P6.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P6DIR.x P6SEL.x OAADC1 OAPMx INCHx
P6.1/A1/OA0O 1 P6.1 (I/O) I: 0; O: 1 0 X 0 X
OA0O (3) X X 1 >0 X
A1 (2) X 1 X 0 1
P6.3/A3/OA1O 3 P6.3 (I/O) I: 0; O: 1 0 X 0 X
OA1O (3) X X 1 >0 X
A3 (2) X 1 X 0 3
P6.5/A5/OA2O 5 P6.5 (I/O) I: 0; O: 1 0 X 0 X
OA2O (3) X X 1 >0 X
A5 (2) X 1 X 0 5
(1) X = don't care
(2) Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.
(3) Setting the OAADC1 bit or setting OAFCx = 00 will cause the operational amplifier to be present at the pin as well as internally connected to the corresponding ADC12 input.

6.10.15 Port P6, P6.6, Input/Output With Schmitt Trigger

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_app15.gif

Table 6-26 Port P6 (P6.6) Pin Functions

PIN NAME (P6.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P6DIR.x P6SEL.x INCHx DAC12.0OPS DAC12.0AMPx OAPx (OA2)
OANx (OA2)
P6.6/A6/DAC0/OA2I0 6 P6.6 (I/O) I: 0; O: 1 0 X 1 X X
DAC0 high impedance X X X 0 0 X
DVSS X X X 0 1 X
DAC0 output X X X 0 >1 X
A6 (2) X 1 6 X X X
OA2I0 0 X 0 X X 0
(1) X = don't care
(2) Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.

6.10.16 Port P6, P6.7, Input/Output With Schmitt Trigger

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_app16.gif

Table 6-27 Port P6 (P6.7) Pin Functions

PIN NAME (P6.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P6DIR.x P6SEL.x INCHx DAC12.1OPS DAC12.1AMPx
P6.7/A7/DAC1/SVSIN 7 P6.7 (I/O) I: 0; O: 1 0 X 1 X
DAC1 high impedance X X X 0 0
DVSS X X X 0 1
DAC1 output X X X 0 >1
A7 (2) X 1 7 X X
SVSIN (2) 0 1 0 1 X
(1) X = don't care
(2) Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.

6.10.17 Port P7, P7.0 to P7.3, Input/Output With Schmitt Trigger

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_app17.gif

Table 6-28 Port P7 (P7.0 and P7.1) Pin Functions

PIN NAME (P7.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P7DIR.x P7SEL.x LCDS32
P7.0/UCA0STE/S33 0 P7.0 (I/O) I: 0; O: 1 0 0
USCI_A0.UCA0STE (2) X 1 0
S33(1) X X 1
P7.1/UCA0SIMO/S32 1 P7.1 (I/O) I: 0; O: 1 0 0
USCI_A0.UCA0SIMO (2) X 1 0
S32 X X 1
(1) X = don't care
(2) The pin direction is controlled by the USCI module.

Table 6-29 Port P7 (P7.2 and P7.3) Pin Functions

PIN NAME (P7.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P7DIR.x P7SEL.x LCDS28
P7.2/UCA0SOMI/S31 2 P7.2 (I/O) I: 0; O: 1 0 0
USCI_A0.UCA0SOMI (2) X 1 0
S31 X X 1
P7.3/UCA0CLK/S30 3 P7.3 (I/O) I: 0; O: 1 0 0
USCI_A0.UCA0CLK (2) X 1 0
S30 X X 1
(1) X = don't care
(2) The pin direction is controlled by the USCI module.

6.10.18 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_app18.gif

Table 6-30 Port P7 (P7.4 and P7.5) Pin Functions

PIN NAME (P7.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P7DIR.x P7SEL.x LCDS28
P7.4/S29 4 P7.4 (I/O) I: 0; O: 1 0 0
S29 X X 1
P7.5/S28 5 P7.5 (I/O) I: 0; O: 1 0 0
S28 X X 1
(1) X = don't care

Table 6-31 Port P7 (P7.6 and P7.7) Pin Functions

PIN NAME (P7.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P7DIR.x P7SEL.x LCDS24
P7.6/S27 6 P7.6 (I/O) I: 0; O: 1 0 0
S27 X X 1
P7.7/S26 7 P7.7 (I/O) I: 0; O: 1 0 0
S26 X X 1
(1) X = don't care

6.10.19 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_app19.gif

Table 6-32 Port P8 (P8.0 and P8.1) Pin Functions

PIN NAME (P8.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P8DIR.x P8SEL.x LCDS16
P8.0/S18 0 P8.0 (I/O) I: 0; O: 1 0 0
S18 X X 1
P8.1/S19 0 P8.0 (I/O) I: 0; O: 1 0 0
S19 X X 1
(1) X = don't care

Table 6-33 Port P8 (P8.2 to P8.5) Pin Functions

PIN NAME (P8.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P8DIR.x P8SEL.x LCDS20
P8.2/S20 2 P8.2 (I/O) I: 0; O: 1 0 0
S20 X X 1
P8.3/S21 3 P8.3 (I/O) I: 0; O: 1 0 0
S21 X X 1
P8.4/S22 4 P8.4 (I/O) I: 0; O: 1 0 0
S22 X X 1
P8.5/S23 5 P8.5 (I/O) I: 0; O: 1 0 0
S23 X X 1
(1) X = don't care

Table 6-34 Port P8 (P8.6 and P8.7) Pin Functions

PIN NAME (P8.x) X FUNCTION CONTROL BITS OR SIGNALS(1)
P8DIR.x P8SEL.x LCDS24
P8.6/S24 6 P8.6 (I/O) I: 0; O: 1 0 0
S24 X X 1
P8.7/S25 7 P8.7 (I/O) I: 0; O: 1 0 0
S25 X X 1
(1) X = don't care

6.10.20 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_app20.gif

Table 6-35 Port P9 (P9.0 and P9.1) Pin Functions

PIN NAME (P9.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P9DIR.x P9SEL.x LCDS16
P9.0/S17 0 P9.0 (I/O) I: 0; O: 1 0 0
S17 X X 1
P9.1/S16 1 P9.1 (I/O) I: 0; O: 1 0 0
S16 X X 1
(1) X = don't care

Table 6-36 Port P9 (P9.2 to P9.5) Pin Functions

PIN NAME (P9.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P9DIR.x P9SEL.x LCDS12
P9.2/S15 2 P9.2 (I/O) I: 0; O: 1 0 0
S15 X X 1
P9.3/S14 3 P9.3 (I/O) I: 0; O: 1 0 0
S14 X X 1
P9.4/S13 4 P9.4 (I/O) I: 0; O: 1 0 0
S13 X X 1
P9.5/S12 5 P9.5 (I/O) I: 0; O: 1 0 0
S12 X X 1
(1) X = don't care

Table 6-37 Port P9 (P9.6 and P9.7) Pin Functions

PIN NAME (P9.x x FUNCTION CONTROL BITS OR SIGNALS(1)
P9DIR.x P9SEL.x LCDS8
P9.6/S11 6 P9.6 (I/O) I: 0; O: 1 0 0
S11 X X 1
P9.7/S10 7 P9.7 (I/O) I: 0; O: 1 0 0
S10 X X 1
(1) X = don't care

6.10.21 Port P10, P10.0 to P10.5, Input/Output With Schmitt Trigger

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_app21.gif

Table 6-38 Port P10 (P10.0 and P10.1) Pin Functions

PIN NAME (P10.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P10DIR.x P10SEL.x LCDS8
P10.0/S9 0 P10.0 (I/O) I: 0; O: 1 0 0
S9 X X 1
P10.1/S8 1 P10.1 (I/O) I: 0; O: 1 0 0
S8 X X 1
(1) X = don't care

Table 6-39 Port P10 (P10.2 to P10.5) Pin Functions

PIN NAME (P10.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P10DIR.x P10SEL.x LCDS4
P10.2/S7 2 P10.2 (I/O) I: 0; O: 1 0 0
S7 X X 1
P10.3/S6 3 P10.3 (I/O) I: 0; O: 1 0 0
S6 X X 1
P10.4/S5 4 P10.4 (I/O) I: 0; O: 1 0 0
S5 X X 1
P10.5/S4 5 P10.5 (I/O) I: 0; O: 1 0 0
S4 X X 1
(1) X = don't care

6.10.22 Port P10, P10.6, Input/Output With Schmitt Trigger

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_app22.gif

Table 6-40 Port P10 (P10.6) Pin Functions

PIN NAME (P10.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P10DIR.x P10SEL.x INCHx LCDS0
P10.6/S3/A15 6 P5.0 (I/O) I: 0; O: 1 0 X 0
A15 (2) X 1 15 0
S3 enabled X 0 X 1
S3 disabled X 1 X 1
(1) X = don't care
(2) Setting the P10SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.

6.10.23 Port P10, P10.7, Input/Output With Schmitt Trigger

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_app23.gif

Table 6-41 Port P10 (P10.7) Pin Functions

PIN NAME (P10.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P10DIR.x P10SEL.x INCHx OAPx (OA1)
OANx (OA1)
LCDS0
P10.7/S2/A14/OA2I1 7 P10.7(I/O) I: 0; O: 1 0 X X 0
A14 (2) X 1 14 X 0
OA2I1 (2) 0 X X 1 0
S2 enabled X 0 X X 1
S2 disabled X 1 X X 1
(1) X = don't care
(2) Setting the P10SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.

6.10.24 VeREF+/DAC0

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_veref_daco.gif

6.10.25 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger or Output

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_jtag_pins.gif

6.10.26 JTAG Fuse Check Mode

Devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current (I(TF)) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.

Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated.

The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see Figure 6-1). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). The JTAG pins are terminated internally and therefore do not require external termination.

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_fuse_ckmode_cur.gifFigure 6-1 Fuse Check Mode Current