SLAS508J April   2006  – June 2015 MSP430FG4616 , MSP430FG4617 , MSP430FG4618 , MSP430FG4619

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3 Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Supply Current Into AVCC + DVCC Excluding External Current
    5. 5.5  Thermal Characteristics
    6. 5.6  Schmitt-Trigger Inputs - Ports P1 to P10, RST/NMI, JTAG (TCK, TMS, TDI/TCLK,TDO/TDI)
    7. 5.7  Inputs Px.x, TAx, TBX
    8. 5.8  Leakage Current - Ports P1 to P10
    9. 5.9  Outputs - Ports P1 to P10
    10. 5.10 Output Frequency
    11. 5.11 Typical Characteristics - Outputs
    12. 5.12 Wake-up Timing From LPM3
    13. 5.13 RAM
    14. 5.14 LCD_A
    15. 5.15 Comparator_A
    16. 5.16 Typical Characteristics - Comparator_A
    17. 5.17 POR, BOR
    18. 5.18 SVS (Supply Voltage Supervisor and Monitor)
    19. 5.19 DCO
    20. 5.20 Crystal Oscillator, LFXT1 Oscillator
    21. 5.21 Crystal Oscillator, XT2 Oscillator
    22. 5.22 USCI (UART Mode)
    23. 5.23 USCI (SPI Master Mode)
    24. 5.24 USCI (SPI Slave Mode)
    25. 5.25 USCI (I2C Mode)
    26. 5.26 USART1
    27. 5.27 12-Bit ADC, Power Supply and Input Range Conditions
    28. 5.28 12-Bit ADC, External Reference
    29. 5.29 12-Bit ADC, Built-In Reference
    30. 5.30 12-Bit ADC, Timing Parameters
    31. 5.31 12-Bit ADC, Linearity Parameters
    32. 5.32 12-Bit ADC, Temperature Sensor and Built-In VMID
    33. 5.33 12-Bit DAC, Supply Specifications
    34. 5.34 12-Bit DAC, Linearity Specifications
    35. 5.35 12-Bit DAC, Output Specifications
    36. 5.36 12-Bit DAC, Reference Input Specifications
    37. 5.37 12-Bit DAC, Dynamic Specifications
    38. 5.38 12-Bit DAC, Dynamic Specifications Continued
    39. 5.39 Operational Amplifier OA, Supply Specifications
    40. 5.40 Operational Amplifier OA, Input/Output Specifications
    41. 5.41 Operational Amplifier OA, Dynamic Specifications
    42. 5.42 Operational Amplifier OA, Typical Characteristics
    43. 5.43 Operational Amplifier OA Feedback Network, Noninverting Amplifier Mode (OAFCx = 4)
    44. 5.44 Operational Amplifier OA Feedback Network, Inverting Amplifier Mode (OAFCx = 6)
    45. 5.45 Flash Memory (FG461x Devices Only)
    46. 5.46 JTAG Interface
    47. 5.47 JTAG Fuse
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Special Function Registers (SFRs)
      1. 6.5.1 Interrupt Enable 1 and 2
      2. 6.5.2 Interrupt Flag Register 1 and 2
      3. 6.5.3 Module Enable Registers 1 and 2
    6. 6.6  Memory Organization
    7. 6.7  Bootstrap Loader (BSL)
    8. 6.8  Flash Memory
    9. 6.9  Peripherals
      1. 6.9.1  DMA Controller
      2. 6.9.2  Oscillator and System Clock
      3. 6.9.3  Brownout, Supply Voltage Supervisor (SVS)
      4. 6.9.4  Digital I/O
      5. 6.9.5  Basic Timer1 and Real-Time Clock
      6. 6.9.6  LCD_A Drive With Regulated Charge Pump
      7. 6.9.7  Watchdog Timer (WDT+)
      8. 6.9.8  Universal Serial Communication Interface (USCI)
      9. 6.9.9  USART1
      10. 6.9.10 Hardware Multiplier
      11. 6.9.11 Timer_A3
      12. 6.9.12 Timer_B7
      13. 6.9.13 Comparator_A
      14. 6.9.14 ADC12
      15. 6.9.15 DAC12
      16. 6.9.16 OA
      17. 6.9.17 Peripheral File Map
    10. 6.10 Input/Output Schematics
      1. 6.10.1  Port P1, P1.0 to P1.5, Input/Output With Schmitt Trigger
      2. 6.10.2  Port P1, P1.6, P1.7, Input/Output With Schmitt Trigger
      3. 6.10.3  Port P2, P2.0 to P2.3, P2.6 to P2.7, Input/Output With Schmitt Trigger
      4. 6.10.4  Port P2, P2.4 to P2.5, Input/Output With Schmitt Trigger
      5. 6.10.5  Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger
      6. 6.10.6  Port P3, P3.4 to P3.7, Input/Output With Schmitt Trigger
      7. 6.10.7  Port P4, P4.0 to P4.1, Input/Output With Schmitt Trigger
      8. 6.10.8  Port P4, P4.2 to P4.7, Input/Output With Schmitt Trigger
      9. 6.10.9  Port P5, P5.0, Input/Output With Schmitt Trigger
      10. 6.10.10 Port P5, P5.1, Input/Output With Schmitt Trigger
      11. 6.10.11 Port P5, P5.2 to P5.4, Input/Output With Schmitt Trigger
      12. 6.10.12 Port P5, P5.5 to P5.7, Input/Output With Schmitt Trigger
      13. 6.10.13 Port P6, P6.0, P6.2, and P6.4, Input/Output With Schmitt Trigger
      14. 6.10.14 Port P6, P6.1, P6.3, and P6.5 Input/Output With Schmitt Trigger
      15. 6.10.15 Port P6, P6.6, Input/Output With Schmitt Trigger
      16. 6.10.16 Port P6, P6.7, Input/Output With Schmitt Trigger
      17. 6.10.17 Port P7, P7.0 to P7.3, Input/Output With Schmitt Trigger
      18. 6.10.18 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
      19. 6.10.19 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
      20. 6.10.20 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
      21. 6.10.21 Port P10, P10.0 to P10.5, Input/Output With Schmitt Trigger
      22. 6.10.22 Port P10, P10.6, Input/Output With Schmitt Trigger
      23. 6.10.23 Port P10, P10.7, Input/Output With Schmitt Trigger
      24. 6.10.24 VeREF+/DAC0
      25. 6.10.25 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger or Output
      26. 6.10.26 JTAG Fuse Check Mode
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Getting Started and Next Steps
      2. 7.1.2 Development Tools Support
        1. 7.1.2.1 Hardware Features
        2. 7.1.2.2 Recommended Hardware Options
          1. 7.1.2.2.1 Target Socket Boards
          2. 7.1.2.2.2 Experimenter Boards
          3. 7.1.2.2.3 Debugging and Programming Tools
          4. 7.1.2.2.4 Production Programmers
        3. 7.1.2.3 Recommended Software Options
          1. 7.1.2.3.1 Integrated Development Environments
          2. 7.1.2.3.2 MSP430Ware
          3. 7.1.2.3.3 Command-Line Programmer
      3. 7.1.3 Device and Development Tool Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Related Links
    4. 7.4 Community Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Export Control Notice
    8. 7.8 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

4 Terminal Configuration and Functions

4.1 Pin Diagrams

Figure 4-1 shows the pinout for the 100-pin PZ package.

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_pinout_pz100.gifFigure 4-1 100-Pin PZ Package (Top View)

Figure 4-2 shows the pinout for the 113-pin ZQW package. This figure shows only the default pin assignments; for all pin assignments, see Table 4-1.

MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_pinout_zqw113.gif
N/A = Not Assigned. All unassigned ball locations on the ZQW package should be electrically tied to the ground supply. The shortest ground return path to the device should be established to ball location B3, DVSS1.
Figure 4-2 113-Pin ZQW Package (Top View)

4.2 Signal Descriptions

Table 4-1 describes the signals for all device variants and package options.

Table 4-1 Signal Descriptions

SIGNAL NAME PIN NO. I/O DESCRIPTION
PZ ZQW
DVCC1 1 A1 Digital supply voltage, positive terminal
P6.3 2 B1 I/O General-purpose digital I/O
A3 Analog input A3 for 12-bit ADC
OA1O OA1 output
P6.4 3 B2 I/O General-purpose digital I/O
A4 Analog input A4 for 12-bit ADC
OA1I0 OA1 input multiplexer on + terminal and – terminal
P6.5 4 C2 I/O General-purpose digital I/O
A5 Analog input A5 for 12-bit ADC
OA2O OA2 output
P6.6 5 C1 I/O General-purpose digital I/O
A6 Analog input A6 for 12-bit ADC
DAC0 DAC12.0 output
OA2I0 OA2 input multiplexer on + terminal and – terminal
P6.7 6 C3 I/O General-purpose digital I/O
A7 Analog input A7 for 12-bit ADC
DAC1 DAC12.1 output
SVSIN Analog input to brownout, supply voltage supervisor
VREF+ 7 D2 O Output of positive terminal of the reference voltage in the ADC
XIN 8 D1 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT 9 E1 O Output terminal of crystal oscillator XT1
VeREF+ 10 E2 I/O Input for an external reference voltage to the ADC
DAC0 DAC12.0 output
VREF 11 E4 I Internal reference voltage, negative terminal for the ADC reference voltage
VeREF– External applied reference voltage, negative terminal for the ADC reference voltage
P5.1 12 F1 I/O General-purpose digital I/O
S0(1) LCD segment output 0
A12 Analog input A12 for 12-bit ADC
DAC1 DAC12.1 output
P5.0 13 F2 I/O General-purpose digital I/O
S1(1) LCD segment output 1
A13 Analog input A13 for 12-bit ADC
OA1I1 OA1 input multiplexer on + terminal and – terminal
P10.7 14 E5 I/O General-purpose digital I/O
S2(1) LCD segment output 2
A14 Analog input A14 for 12-bit ADC
OA2I1 OA2 input multiplexer on + terminal and – terminal
P10.6 15 G1 I/O General-purpose digital I/O
S3(1) LCD segment output 3
A15 Analog input A15 to 12-bit ADC
P10.5 16 G2 I/O General-purpose digital I/O
S4 LCD segment output 4
P10.4 17 F4 I/O General-purpose digital I/O
S5 LCD segment output 5
P10.3 18 H1 I/O General-purpose digital I/O
S6 LCD segment output 6
P10.2 19 H2 I/O General-purpose digital I/O
S7 LCD segment output 7
P10.1 20 F5 I/O General-purpose digital I/O
S8 LCD segment output 8
P10.0 21 J1 I/O General-purpose digital I/O
S9 LCD segment output 9
P9.7 22 J2 I/O General-purpose digital I/O
S10 LCD segment output 10
P9.6 23 G4 I/O General-purpose digital I/O
S11 LCD segment output 11
P9.5 24 K1 I/O General-purpose digital I/O
S12 LCD segment output 12
P9.4 25 L1 I/O General-purpose digital I/O
S13 LCD segment output 13
P9.3 26 M2 I/O General-purpose digital I/O
S14 LCD segment output 14
P9.2 27 K2 I/O General-purpose digital I/O
S15 LCD segment output 15
P9.1 28 L3 I/O General-purpose digital I/O
S16 LCD segment output 16
P9.0 29 M3 I/O General-purpose digital I/O
S17 LCD segment output 17
P8.7 30 H4 I/O General-purpose digital I/O
S18 LCD segment output 18
P8.6 31 L4 I/O General-purpose digital I/O
S19 LCD segment output 19
P8.5 32 M4 I/O General-purpose digital I/O
S20 LCD segment output 20
P8.4 33 G5 I/O General-purpose digital I/O
S21 LCD segment output 21
P8.3 34 L5 I/O General-purpose digital I/O
S22 LCD segment output 22
P8.2 35 M5 I/O General-purpose digital I/O
S23 LCD segment output 23
P8.1 36 H5 I/O General-purpose digital I/O
S24 LCD segment output 24
P8.0 37 J5 I/O General-purpose digital I/O
S25 LCD segment output 25
P7.7 38 M6 I/O General-purpose digital I/O
S26 LCD segment output 26
P7.6 39 L6 I/O General-purpose digital I/O
S27 LCD segment output 27
P7.5 40 J6 I/O General-purpose digital I/O
S28 LCD segment output 28
P7.4 41 M7 I/O General-purpose digital I/O
S29 LCD segment output 29
P7.3 42 H6 I/O General-purpose digital I/O
UCA0CLK External clock input – USCI_A0 in UART or SPI mode,
Clock output – USCI_A0 in SPI mode
S30 LCD segment 30
P7.2 43 L7 I/O General-purpose digital I/O
UCA0SOMI Slave out/master in of USCI_A0 in SPI mode
S31 LCD segment output 31
P7.1 44 M8 I/O General-purpose digital I/O
UCA0SIMO Slave in/master out of USCI_A0 in SPI mode
S32 LCD segment output 32
P7.0 45 L8 I/O General-purpose digital I/O
UCA0STE Slave transmit enable – USCI_A0 in SPI mode
S33 LCD segment output 33
P4.7 46 J7 I/O General-purpose digital I/O
UCA0RXD Receive data in – USCI_A0 in UART or IrDA mode
S34 LCD segment output 34
P4.6 47 M9 I/O General-purpose digital I/O
UCA0TXD Transmit data out – USCI_A0 in UART or IrDA mode
S35 LCD segment output 35
P4.5 48 L9 I/O General-purpose digital I/O
UCLK1 External clock input – USART1 in UART or SPI mode,
Clock output – USART1 in SPI MODE
S36 LCD segment output 36
P4.4 49 H7 I/O General-purpose digital I/O
SOMI1 Slave out/master in of USART1 in SPI mode
S37 LCD segment output 37
P4.3 50 M10 I/O General-purpose digital I/O
SIMO1 Slave in/master out of USART1 in SPI mode
S38 LCD segment output 38
P4.2 51 M11 I/O General-purpose digital I/O
STE1 Slave transmit enable – USART1 in SPI mode
S39 LCD segment output 39
COM0 52 L10 O Common output, COM0 for LCD backplanes
P5.2 53 L12 I/O General-purpose digital I/O
COM1 Common output, COM1 for LCD backplanes
P5.3 54 J8 I/O General-purpose digital I/O
COM2 Common output, COM2 for LCD backplanes
P5.4 55 K12 I/O General-purpose digital I/O
COM3 Common output, COM3 for LCD backplanes
P5.5 56 K11 I/O General-purpose digital I/O
R03 Input port of lowest analog LCD level (V5)
P5.6 57 J12 I/O General-purpose digital I/O
LCDREF External reference voltage input for regulated LCD voltage
R13 Input port of third most positive analog LCD level (V4 or V3)
P5.7 58 J11 I/O General-purpose digital I/O
R23 Input port of second most positive analog LCD level (V2)
LCDCAP 59 H11 I LCD capacitor connection
R33 Input/output port of most positive analog LCD level (V1)
DVCC2 60 H12 Digital supply voltage, positive terminal
DVSS2 61 G12 Digital supply voltage, negative terminal
P4.1 62 G11 I/O General-purpose digital I/O
URXD1 Receive data in – USART1 in UART mode
P4.0 63 H9 I/O General-purpose digital I/O
UTXD1 Transmit data out – USART1 in UART mode
P3.7 64 F12 I/O General-purpose digital I/O
TB6 Timer_B7 CCR6. Capture: CCI6A/CCI6B input, compare: Out6 output
P3.6 65 F11 I/O General-purpose digital I/O
TB5 Timer_B7 CCR5. Capture: CCI5A/CCI5B input, compare: Out5 output
P3.5 66 G9 I/O General-purpose digital I/O
TB4 Timer_B7 CCR4. Capture: CCI4A/CCI4B input, compare: Out4 output
P3.4 67 E12 I/O General-purpose digital I/O
TB3 Timer_B7 CCR3. Capture: CCI3A/CCI3B input, compare: Out3 output
P3.3 68 E11 I/O General-purpose digital I/O
UCB0CLK External clock input – USCI_B0 in UART or SPI mode,
Clock output – USCI_B0 in SPI mode
P3.2 69 F9 I/O General-purpose digital I/O
UCB0SOMI Slave out/master in of USCI_B0 in SPI mode
UCB0SCL I2C clock – USCI_B0 in I2C mode
P3.1 70 D12 I/O General-purpose digital I/O
UCB0SIMO Slave in/master out of USCI_B0 in SPI mode
UCB0SDA I2C data – USCI_B0 in I2C mode
P3.0 71 D11 I/O General-purpose digital I/O
UCB0STE Slave transmit enable – USCI_B0 in SPI mode
P2.7 72 E9 I/O General-purpose digital I/O
ADC12CLK Conversion clock for 12-bit ADC
DMAE0 DMA channel 0 external trigger
P2.6 73 C12 I/O General-purpose digital I/O
CAOUT Comparator_A output
P2.5 74 C11 I/O General-purpose digital I/O
UCA0RXD Receive data in – USCI_A0 in UART or IrDA mode
P2.4 75 B12 I/O General-purpose digital I/O
UCA0TXD Transmit data out – USCI_A0 in UART or IrDA mode
P2.3 76 A11 I/O General-purpose digital I/O
TB2 Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2 77 E8 I/O General-purpose digital I/O
TB1 Timer_B7 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1 78 D8 I/O General-purpose digital I/O
TB0 Timer_B7 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0 79 A10 I/O General-purpose digital I/O
TA2 Timer_A Capture: CCI2A input, compare: Out2 output
P1.7 80 B10 I/O General-purpose digital I/O
CA1 Comparator_A input
P1.6 81 A9 I/O General-purpose digital I/O
CA0 Comparator_A input
P1.5 82 B9 I/O General-purpose digital I/O
TACLK Timer_A, clock signal TACLK input
ACLK ACLK output (divided by 1, 2, 4, or 8)
P1.4 83 B8 I/O General-purpose digital I/O
TBCLK Input clock TBCLK – Timer_B7
SMCLK Submain system clock SMCLK output
P1.3 84 A8 I/O General-purpose digital I/O
TBOUTH Switch all PWM digital output ports to high impedance – Timer_B7 TB0 to TB6
SVSOUT SVS: output of SVS comparator
P1.2 85 D7 I/O General-purpose digital I/O
TA1 Timer_A, Capture: CCI1A input, compare: Out1 output
P1.1 86 E7 I/O General-purpose digital I/O
TA0 Timer_A. Capture: CCI0B input. Note: TA0 is only an input on this pin. BSL receive.
MCLK MCLK output
P1.0 87 A7 I/O General-purpose digital I/O
TA0 Timer_A. Capture: CCI0A input, compare: Out0 output. BSL transmit.
XT2OUT 88 B7 O Output terminal of crystal oscillator XT2
XT2IN 89 B6 I Input port for crystal oscillator XT2. Only standard crystals can be connected.
TDO 90 A6 I/O Test data output port. TDO/TDI data output.
TDI Programming data input terminal
TDI 91 D6 I Test data input
TCLK Test clock input. The device protection fuse is connected to TDI/TCLK.
TMS 92 E6 I Test mode select. TMS is used as an input port for device programming and test.
TCK 93 A5 I Test clock. TCK is the clock input port for device programming and test.
RST 94 B5 I Reset input
NMI Nonmaskable interrupt input port
P6.0 95 A4 I/O General-purpose digital I/O
A0 Analog input A0 for 12-bit ADC
OA0I0 OA0 input multiplexer on + terminal and – terminal
P6.1 96 D5 I/O General-purpose digital I/O
A1 Analog input A1 for 12-bit ADC
OA0O OA0 output
P6.2 97 B4 I/O General-purpose digital I/O
A2 Analog input A2 for 12-bit ADC
OA0I1 OA0 input multiplexer on + terminal and – terminal
AVSS 98 A3 Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, Comparator_A, port 1
DVSS1 99 B3 Digital supply voltage, negative terminal
AVCC 100 A2 Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, Comparator_A, port 1. Do not power up before powering DVCC1 and DVCC2.
Not Assigned A12, B11, D4, D9, F8, G8, H8, J4, J9, L2, L11, M1, M12 All unassigned ball locations on the ZQW package should be electrically tied to the ground supply. The shortest ground return path to the device should be established to ball location B3, DVSS1.
(1) Segments S0 through S3 are disabled when the LCD charge pump feature is enabled (LCDCPEN = 1) and, therefore, cannot be used together with the LCD charge pump. On the MSP430xG461x devices only, S0 through S3 are also disabled if VLCDEXT = 1. This setting is typically used to apply an external LCD voltage supply to the LCDCAP terminal. For these devices, set LCDCPEN = 0, VLCDEXT = 0, and VLCDx > 0 to enable an external LCD voltage supply to be applied to the LCDCAP terminal.