JAJSEE2B January   2018  – August 2019 MSP430FR2512 , MSP430FR2522

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Types
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1       Absolute Maximum Ratings
    2. 5.2       ESD Ratings
    3. 5.3       Recommended Operating Conditions
    4. 5.4       Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5       Active Mode Supply Current Per MHz
    6. 5.6       Low-Power Mode (LPM0) Supply Currents Into VCC Excluding External Current
    7. 5.7       Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8       Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    9. 5.9       Typical Characteristics - Low-Power Mode Supply Currents
    10. Table 5-1 Typical Characteristics – Current Consumption Per Module
    11. 5.10      Thermal Resistance Characteristics
    12. 5.11      Timing and Switching Characteristics
      1. 5.11.1  Power Supply Sequencing
        1. Table 5-2 PMM, SVS and BOR
      2. 5.11.2  Reset Timing
        1. Table 5-3 Wake-up Times From Low-Power Modes and Reset
      3. 5.11.3  Clock Specifications
        1. Table 5-4 XT1 Crystal Oscillator (Low Frequency)
        2. Table 5-5 DCO FLL, Frequency
        3. Table 5-6 DCO Frequency
        4. Table 5-7 REFO
        5. Table 5-8 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. Table 5-9 Module Oscillator (MODOSC)
      4. 5.11.4  Digital I/Os
        1. Table 5-10 Digital Inputs
        2. Table 5-11 Digital Outputs
        3. 5.11.4.1   Typical Characteristics – Outputs at 3 V and 2 V
      5. 5.11.5  VREF+ Built-in Reference
        1. Table 5-12 VREF+
      6. 5.11.6  Timer_A
        1. Table 5-13 Timer_A
      7. 5.11.7  eUSCI
        1. Table 5-14 eUSCI (UART Mode) Clock Frequency
        2. Table 5-15 eUSCI (UART Mode)
        3. Table 5-16 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-17 eUSCI (SPI Master Mode)
        5. Table 5-18 eUSCI (SPI Slave Mode)
        6. Table 5-19 eUSCI (I2C Mode)
      8. 5.11.8  ADC
        1. Table 5-20 ADC, Power Supply and Input Range Conditions
        2. Table 5-21 ADC, 10-Bit Timing Parameters
        3. Table 5-22 ADC, 10-Bit Linearity Parameters
      9. 5.11.9  CapTIvate
        1. Table 5-23 CapTIvate Electrical Characteristics
        2. Table 5-24 CapTIvate Signal-to-Noise Ratio Characteristics
      10. 5.11.10 FRAM
        1. Table 5-25 FRAM
      11. 5.11.11 Debug and Emulation
        1. Table 5-26 JTAG, Spy-Bi-Wire Interface
        2. Table 5-27 JTAG, 4-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Standard Interface
    7. 6.7  Spy-Bi-Wire Interface (SBW)
    8. 6.8  FRAM
    9. 6.9  Memory Protection
    10. 6.10 Peripherals
      1. 6.10.1  Power-Management Module (PMM)
      2. 6.10.2  Clock System (CS) and Clock Distribution
      3. 6.10.3  General-Purpose Input/Output Port (I/O)
      4. 6.10.4  Watchdog Timer (WDT)
      5. 6.10.5  System (SYS) Module
      6. 6.10.6  Cyclic Redundancy Check (CRC)
      7. 6.10.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 6.10.8  Timers (Timer0_A3, Timer1_A3)
      9. 6.10.9  Hardware Multiplier (MPY)
      10. 6.10.10 Backup Memory (BAKMEM)
      11. 6.10.11 Real-Time Clock (RTC)
      12. 6.10.12 10-Bit Analog-to-Digital Converter (ADC)
      13. 6.10.13 CapTIvate Technology
      14. 6.10.14 Embedded Emulation Module (EEM)
    11. 6.11 Input/Output Diagrams
      1. 6.11.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.11.2 Port P2 (P2.0 to P2.6) Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors
    13. 6.13 Memory
      1. 6.13.1 Memory Organization
      2. 6.13.2 Peripheral File Map
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
      2. 7.2.2 CapTIvate Peripheral
        1. 7.2.2.1 Device Connection and Layout Fundamentals
        2. 7.2.2.2 Measurements
          1. 7.2.2.2.1 SNR
          2. 7.2.2.2.2 Sensitivity
          3. 7.2.2.2.3 Power
    3. 7.3 CapTIvate Technology Evaluation
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1  使い始めと次の手順
    2. 8.2  デバイスの項目表記
    3. 8.3  ツールとソフトウェア
    4. 8.4  ドキュメントのサポート
    5. 8.5  関連リンク
    6. 8.6  Community Resources
    7. 8.7  商標
    8. 8.8  静電気放電に関する注意事項
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • PW|16
  • RHL|20
サーマルパッド・メカニカル・データ
発注情報

Signal Descriptions

Table 4-2 describes the signals for all device variants and package options.

Table 4-2 Signal Descriptions

FUNCTION SIGNAL NAME PIN NUMBER PIN TYPE(1) DESCRIPTION
RHL PW
ADC A0 2 2 I Analog input A0
A1 1 1 I Analog input A1
A2 20 16 I Analog input A2
A3 19 15 I Analog input A3
A4 11 9 I Analog input A4
A5 12 I Analog input A5
A6 9 I Analog input A6
A7 13 I Analog input A7
Veref+ 2 2 I ADC positive reference
Veref- 20 16 I ADC negative reference
CapTIvate CAP0.0 17 13 I/O CapTIvate channel
CAP0.1 16 12 I/O CapTIvate channel
CAP0.2 15 11 I/O CapTIvate channel
CAP0.3 14 10 I/O CapTIvate channel
CAP1.0(2) 2 2 I/O CapTIvate channel
CAP1.1(2) 1 1 I/O CapTIvate channel
CAP1.2(2) 20 16 I/O CapTIvate channel
CAP1.3(2) 19 15 I/O CapTIvate channel
SYNC 13 9 I CapTIvate synchronous trigger input for processing and conversion
Clock ACLK 1 1 I/O ACLK output
MCLK 19 15 O MCLK output
SMCLK 20 16 O SMCLK output
XIN 7 7 I Input terminal for crystal oscillator
XOUT 8 8 O Output terminal for crystal oscillator
Debug SBWTCK 3 3 I Spy-Bi-Wire input clock
SBWTDIO 4 4 I/O Spy-Bi-Wire data input/output
TCK 17 13 I Test clock
TCLK 15 11 I Test clock input
TDI 15 11 I Test data input
TDO 14 10 O Test data output
TEST 3 3 I Test mode pin – selected digital I/O on JTAG pins
TMS 16 12 I Test mode select
GPIO P1.0 2 2 I/O General-purpose I/O
P1.1 1 1 I/O General-purpose I/O
P1.2 20 16 I/O General-purpose I/O
P1.3 19 15 I/O General-purpose I/O
P1.4 17 13 I/O General-purpose I/O(5)
P1.5 16 12 I/O General-purpose I/O(5)
P1.6 15 11 I/O General-purpose I/O(5)
P1.7 14 10 I/O General-purpose I/O(5)
P2.0 8 8 I/O General-purpose I/O
P2.1 7 7 I/O General-purpose I/O
P2.2 13 9 I/O General-purpose I/O
P2.3 12 I/O General-purpose I/O
P2.4 11 I/O General-purpose I/O
P2.5 10 I/O General-purpose I/O
P2.6 9 I/O General-purpose I/O
I2C UCB0SCL(3) 19 15 I/O eUSCI_B0 I2C clock
UCB0SDA(3) 20 16 I/O eUSCI_B0 I2C data
UCB0SCL(3) 9 I/O eUSCI_B0 I2C clock
UCB0SDA(3) 10 I/O eUSCI_B0 I2C data
Power DVCC 5 5 P Power supply
DVSS 6 6 P Power ground
VREF+ 1 1 P Output of positive reference voltage with ground as reference
VREG 18 14 O CapTIvate regulator external decoupling capacitor
SPI UCA0STE 14 10 I/O eUSCI_A0 SPI slave transmit enable
UCA0CLK 15 11 I/O eUSCI_A0 SPI clock input/output
UCA0SOMI(3)(4) 16 12 I/O eUSCI_A0 SPI slave out/master in
UCA0SIMO(3)(4) 17 13 I/O eUSCI_A0 SPI slave in/master out
UCA0SOMI(3)(4) 7 7 I/O eUSCI_A0 SPI slave out/master in
UCA0SIMO(3)(4) 8 8 I/O eUSCI_A0 SPI slave in/master out
UCB0STE(3) 2 2 I/O eUSCI_B0 slave transmit enable
UCB0CLK(3) 1 1 I/O eUSCI_B0 clock input/output
UCB0SOMI(3) 19 15 I/O eUSCI_B0 SPI slave out/master in
UCB0SIMO(3) 20 16 I/O eUSCI_B0 SPI slave in/master out
UCB0STE(3) 12 I/O eUSCI_B0 slave transmit enable
UCB0CLK(3) 11 I/O eUSCI_B0 clock input/output
UCB0SOMI(3) 9 I/O eUSCI_B0 SPI slave out/master in
UCB0SIMO(3) 10 I/O eUSCI_B0 SPI slave in/master out
System NMI 4 4 I Nonmaskable interrupt input
RST 4 4 I Active-low reset input
Timer_A TA0.1 17 13 I/O Timer TA0 CCR1 capture: CCI1A input, compare: Out1 outputs
TA0.2 16 12 I/O Timer TA0 CCR2 capture: CCI2A input, compare: Out2 outputs
TA0CLK 15 11 I Timer clock input TACLK for TA0
TA1.1 13 9 I/O Timer TA1 CCR1 capture: CCI1A input, compare: Out1 outputs
TA1.2 12 I/O Timer TA1 CCR2 capture: CCI2A input, compare: Out2 outputs
TA1CLK 11 I Timer clock input TACLK for TA1
UART UCA0RXD(3) 16 12 I eUSCI_A0 UART receive data
UCA0TXD(3) 17 13 O eUSCI_A0 UART transmit data
UCA0RXD(3) 7 7 I eUSCI_A0 UART receive data
UCA0TXD(3) 8 8 O eUSCI_A0 UART transmit data
QFN Pad QFN thermal pad Pad QFN package exposed thermal pad. TI recommends connecting to VSS.
Pin Types: I = Input, O = Output, I/O = Input or Output, P = Power
MSP430FR2522 only
These signal assignments are controlled by the USCIARMP bit of the SYSCFG3 register or the USCIBRMP bit of the SYSCFG2 register. Only one group can be selected at one time.
Signal assignments on these pins are controlled by the remap functionality and are selected by the USCIARMP bit in the SYSCFG3 register. Only one group can be selected at one time. The CLK and STE assignments are fixed and shared by both SPI function groups.
Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to prevent collisions.