JAJSFI3A May 2018 – November 2018 TAS3251
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSPR | Reserved | RQST | Reserved | RQPD | |||
R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | DSPR | R/W | 1 | DSP reset – When the bit is made 0, DSP will start powering up and send out data. This needs to be made 0 only after all the input clocks are (ASI,MCLK,PLLCLK) are settled so that DMA channels do not go out of sync.
0: Normal operation
|
6-5 | Reserved | R/W | Reserved | |
4 | RQST | R/W | 0 | Standby Request – When this bit is set, the DAC will be forced into a system standby mode, which is also the mode the system enters in the case of clock errors. In this mode, most subsystems will be powered down but the charge pump and digital power supply.
0: Normal operation
|
3-1 | Reserved | R/W | Reserved | |
0 | RQPD | R/W | 0 | Powerdown Request – When this bit is set, the DAC will be forced into powerdown mode, in which the power consumption would be minimum as the charge pump is also powered down. However, it will take longer to restart from this mode. This mode has higher precedence than the standby mode, i.e. setting this bit along with bit 4 for standby mode will result in the DAC going into powerdown mode.
0: Normal operation
|