JAJSFI3A May 2018 – November 2018 TAS3251
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | LTSH | Reserved | CKMF | CSRF | CERF | ||
R/W | R | R/W | R | R | R |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | Reserved | R/W | 0 | Reserved |
4 | LTSH | R | Latched Clock Halt – This bit indicates whether MCLK halt has occurred. The bit is cleared when read.
0: MCLK halt has not occurred
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|
3 | Reserved | R/W | 0 | Reserved |
2 | CKMF | R | Clock Missing – This bit indicates whether the LRCLK and SCLK are missing (tied low).
0: LRCLK and/or SCLK is present
|
|
1 | CSRF | R | Clock Resync Request – This bit indicates whether the clock resynchronization is in progress.
0: Not resynchronizing
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|
0 | CERF | R | Clock Error – This bit indicates whether a clock error has occurred. The bit is cleared when read
0: Clock error has not occurred
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