JAJSF33B August   2017  – July 2018 THS3491


  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      標準的な任意波形発生器の出力駆動回路
      2.      高調波歪みと周波数との関係
  4. 改訂履歴
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = ±15 V
    6. 7.6 Electrical Characteristics: VS = ±7.5 V
    7. 7.7 Typical Characteristics: ±15 V
    8. 7.8 Typical Characteristics: ±7.5 V
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-Down (PD) Pin
      2. 8.3.2 Power-Down Reference (REF) Pin
      3. 8.3.3 Internal Junction Temperature Sense (TJ_SENSE) Pin
    4. 8.4 Device Functional Modes
      1. 8.4.1 Wideband Noninverting Operation
      2. 8.4.2 Wideband, Inverting Operation
      3. 8.4.3 Single-Supply Operation
      4. 8.4.4 Maximum Recommended Output Voltage
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Driving Capacitive Loads
      2. 9.1.2 Video Distribution
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PowerPAD™ Integrated Circuit Package Design Considerations (DDA Package Only)
        1. PowerPAD™ Integrated Circuit Package Layout Considerations
        2. Power Dissipation and Thermal Considerations
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報


  • DDA|8
  • RGT|16

Power-Down (PD) Pin

The THS3491 features a power-down (PD) pin that lowers the quiescent current from 16.7 mA down to 750 µA, which is designed to reduce system power.

The power-down pin of the amplifier defaults to 2 V below the positive supply voltage in the absence of an externally applied voltage, which places the amplifier in the power-on mode of operation. To turn off the amplifier in an effort to conserve power, the power-down pin can be pulled low. The PD pin threshold voltages are specified with respect to the REF pin voltage. The threshold voltages for power on and power down are relative to the REF pin and are shown in the Electrical Characteristics: VS = ±15 V and Electrical Characteristics: VS = ±7.5 V tables. Above the enable threshold voltage, the device is on. Below the disable threshold voltage, the device is off. The behavior is not specified between these threshold voltages.

This power-down functionality helps the amplifier consume less power in power-down mode. Power-down mode is not intended to provide a high-impedance output. The power-down functionality is not intended for use as a tri-state bus driver. In power-down mode, the impedance looking back into the output of the amplifier is dominated by the feedback and gain-setting resistors, but the output impedance of the device varies depending on the voltage applied to the outputs.

As with most current-feedback amplifiers, the internal architecture places limitations on the system in power-down mode. The most common limitation is that the amplifier turns on if there is a ±1 V or greater difference between the two input nodes (VIN+ and VIN–) of the amplifier. If this difference exceeds ±1 V, the amplifier creates an output voltage equal to approximately [(VIN+ – VIN–) –0.7 V] × gain. Conversely if a voltage is applied to the output while in power-down mode, the VIN– node voltage is equal to VO(applied) × RG / (RF + RG). For low-gain configurations and a large applied voltage at the output, the amplifier may turn on because of the aforementioned behavior.

The time delays associated with turning the device on and off are specified as the time it takes for the amplifier to reach 10% or 90% of the final output voltage. The time delays are in nanoseconds during power on and microseconds during power off because the amplifier moves out of linear operating mode for power-off conditions.