JAJSF33B August 2017 – July 2018 THS3491
Applications such as power JFET and MOSFET (power FET) drivers are highly capacitive and cause stability problems for high-speed amplifiers.
Figure 65 and Figure 66 show recommended methods for driving capacitive loads. The basic idea is to use a resistor or ferrite chip to isolate the phase shift at high frequency caused by the capacitive load from the amplifier feedback path. The output impedance of the amplifier in conjunction with CLOAD introduces a pole in the open-loop transimpedance gain response and if the pole is at a frequency lower than the non-dominant pole of the amplifier, then this results in a reduced loop gain and a reduced phase margin. The isolation resistor introduces a zero in the response, which counteracts the effect of the pole. The location of the zero is dependent on the values of RISO and CLOAD. Figure 5 provides examples of recommended RISO values to achieve flat frequency response while driving certain capacitive loads. See Effect of Parasitic Capacitance in Op Amp Circuits for a detailed analysis of selecting isolation resistor values while driving capacitive loads.
Placing a small series resistor (RISO) between the output of the amplifier and the capacitive load as Figure 65 shows is a simple way to isolate the load capacitance.
Figure 66 shows two amplifiers in parallel to double the output drive current in order to drive larger capacitive loads. This technique is used when more output current is required to charge and discharge the load faster, such as driving large FET transistors.
Figure 67 shows a push-pull FET driver circuit commonly used in ultrasound applications with isolation resistors to isolate the gate capacitance from the amplifier.