JAJSF33B August   2017  – July 2018 THS3491

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      標準的な任意波形発生器の出力駆動回路
      2.      高調波歪みと周波数との関係
  4. 改訂履歴
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = ±15 V
    6. 7.6 Electrical Characteristics: VS = ±7.5 V
    7. 7.7 Typical Characteristics: ±15 V
    8. 7.8 Typical Characteristics: ±7.5 V
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-Down (PD) Pin
      2. 8.3.2 Power-Down Reference (REF) Pin
      3. 8.3.3 Internal Junction Temperature Sense (TJ_SENSE) Pin
    4. 8.4 Device Functional Modes
      1. 8.4.1 Wideband Noninverting Operation
      2. 8.4.2 Wideband, Inverting Operation
      3. 8.4.3 Single-Supply Operation
      4. 8.4.4 Maximum Recommended Output Voltage
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Driving Capacitive Loads
      2. 9.1.2 Video Distribution
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PowerPAD™ Integrated Circuit Package Design Considerations (DDA Package Only)
        1. 11.1.1.1 PowerPAD™ Integrated Circuit Package Layout Considerations
        2. 11.1.1.2 Power Dissipation and Thermal Considerations
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
発注情報

Driving Capacitive Loads

Applications such as power JFET and MOSFET (power FET) drivers are highly capacitive and cause stability problems for high-speed amplifiers.

Figure 65 and Figure 66 show recommended methods for driving capacitive loads. The basic idea is to use a resistor or ferrite chip to isolate the phase shift at high frequency caused by the capacitive load from the amplifier feedback path. The output impedance of the amplifier in conjunction with CLOAD introduces a pole in the open-loop transimpedance gain response and if the pole is at a frequency lower than the non-dominant pole of the amplifier, then this results in a reduced loop gain and a reduced phase margin. The isolation resistor introduces a zero in the response, which counteracts the effect of the pole. The location of the zero is dependent on the values of RISO and CLOAD. Figure 5 provides examples of recommended RISO values to achieve flat frequency response while driving certain capacitive loads. See Effect of Parasitic Capacitance in Op Amp Circuits for a detailed analysis of selecting isolation resistor values while driving capacitive loads.

THS3491 SBOS875_THS3491-Large-CLoad-Drive.gifFigure 65. Driving a Large Capacitive Load Using an Output Series Isolation Resistor

Placing a small series resistor (RISO) between the output of the amplifier and the capacitive load as Figure 65 shows is a simple way to isolate the load capacitance.

Figure 66 shows two amplifiers in parallel to double the output drive current in order to drive larger capacitive loads. This technique is used when more output current is required to charge and discharge the load faster, such as driving large FET transistors.

THS3491 SBOS875_THS3491-CLoad-Drive-Parallel-OPAs.gifFigure 66. Driving a Large Capacitive Load Using Two Parallel Amplifier Channels

Figure 67 shows a push-pull FET driver circuit commonly used in ultrasound applications with isolation resistors to isolate the gate capacitance from the amplifier.

THS3491 SBOS875_THS3491-2OPAs-CLoad-FET-Driver.gifFigure 67. Power FET Drive Circuit