JAJSF71A April   2018  – May 2017 TLIN1024-Q1

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      概略回路図
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings - IEC
    4. 6.4 Thermal Information
    5. 6.5 Recommended Operating Conditions
    6. 6.6 Electrical Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  LIN (Local Interconnect Network) Bus
        1. 8.3.1.1 LIN Transmitter Characteristics
        2. 8.3.1.2 LIN Receiver Characteristics
          1. 8.3.1.2.1 Termination
      2. 8.3.2  TXD (Transmit Input/Output)
      3. 8.3.3  RXD (Receive Output)
      4. 8.3.4  VSUP1/2 (Supply Voltage)
      5. 8.3.5  GND (Ground)
      6. 8.3.6  EN (Enable Input)
      7. 8.3.7  Protection Features
      8. 8.3.8  TXD Dominant Time Out (DTO)
      9. 8.3.9  Bus Stuck Dominant System Fault: False Wake Up Lockout
      10. 8.3.10 Thermal Shutdown
      11. 8.3.11 Under Voltage on VSUP
      12. 8.3.12 Unpowered Device and LIN Bus
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Mode
      2. 8.4.2 Sleep Mode
      3. 8.4.3 Standby Mode
      4. 8.4.4 Wake Up Events
        1. 8.4.4.1 Wake Up Request (RXD)
        2. 8.4.4.2 Mode Transitions
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Normal Mode Application Note
        2. 9.2.2.2 Standby Mode Application Note
        3. 9.2.2.3 TXD Dominant State Timeout Application Note
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Parameter Measurement Information

TLIN1024-Q1 ISO17987-2-Test-PG1.gifFigure 8. Test System: Operating Voltage Range with RX and TX Access
TLIN1024-Q1 ISO17987-2-Test-PG1-d.gifFigure 9. RX Response: Operating Voltage Range
TLIN1024-Q1 ISO17987-2-Test-PG1-c.gifFigure 10. LIN Bus Input Signal
TLIN1024-Q1 ISO17987-2-Test-PG1-a.gifFigure 11. LIN Receiver Test with RX Access
TLIN1024-Q1 ISO17987-2-Test-PG1-b.gifFigure 12. VSUP_NON_OP
TLIN1024-Q1 ISO17987-2-Test-PG2.gifFigure 13. Test Circuit for IBUS_LIM at Dominant State (Driver on)
TLIN1024-Q1 ISO17987-2-Test-PG2-a.gifFigure 14. Test Circuit for IBUS_PAS_dom; TXD = Recessive State VBUS = 0 V
TLIN1024-Q1 ISO17987-2-Test-PG2-B.gifFigure 15. Test Circuit for IBUS_PAS_rec
TLIN1024-Q1 ISO17987-2-Test-PG2-D.gifFigure 16. Test Circuit for IBUS_NO_GND Loss of GND
TLIN1024-Q1 ISO17987-2-Test-PG2-E.gifFigure 17. Test Circuit for IBUS_NO_BAT Loss of Battery
TLIN1024-Q1 ISO7987-2-Test-PG3.gifFigure 18. Test Circuit Slope Control and Duty Cycle
TLIN1024-Q1 Bus-Def-Timing.gifFigure 19. Definition of Bus Timing Parameters
TLIN1024-Q1 ISO7987-2-Test-PG3-B.gifFigure 20. Propagation Delay Test Circuit
TLIN1024-Q1 Prop-Delay.gifFigure 21. Propagation Delay
TLIN1024-Q1 Fig-7-15-Mode-Transitions.gifFigure 22. Mode Transitions
TLIN1024-Q1 Fig-7-16-Wake-with-LIN.gifFigure 23. Wake Up Through EN
TLIN1024-Q1 Fig-7-17Wake-with-LIN.gifFigure 24. Wake Up Through LIN
TLIN1024-Q1 Fig-7-19-Test-Circuit-for-AC-Char.gifFigure 25. Test Circuit for AC Characteristics