JAJSEU0G March   2003  – February 2018 TLV2460-Q1 , TLV2460A-Q1 , TLV2461-Q1 , TLV2461A-Q1 , TLV2462-Q1 , TLV2462A-Q1 , TLV2463-Q1 , TLV2463A-Q1 , TLV2464A-Q1

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     代表的なアプリケーション
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
    2.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information: TLV2460x-Q1
    5. 6.5  Thermal Information: TLV2461x-Q1
    6. 6.6  Thermal Information: TLV2462-Q1
    7. 6.7  Thermal Information: TLV2462A-Q1
    8. 6.8  Thermal Information: TLV2463x-Q1
    9. 6.9  Electrical Characteristics: VDD = 3 V
    10. 6.10 Electrical Characteristics: VDD = 5 V
    11. 6.11 Operating Characteristics: VDD = 3 V
    12. 6.12 Operating Characteristics: VDD = 5 V
    13. 6.13 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Driving a Capacitive Load
      2. 8.3.2 Offset Voltage
      3. 8.3.3 General Configurations
      4. 8.3.4 General Power Dissipation Considerations
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Function
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Macromodel Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • PW|8
サーマルパッド・メカニカル・データ
発注情報

Detailed Design Procedure

The following section shows the detailed design procedure. See Equation 2 for the type-3 compensation gain.

Equation 2. TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463-Q1 TLV2463A-Q1 TLV2464A-Q1 pe3compgain_gls008.gif

Type-3 compensation poles and zeros are shown in the preferred asymptotic graph; see Figure 56. Relocate the compensation poles and zeroes by changing the values of the resistors and capacitors according to the compensation requirement. The operational amplifier cannot achieve the preferred case because of the open-loop gain and phase limitation of the amplifier.

TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463-Q1 TLV2463A-Q1 TLV2464A-Q1 compgain_gls008.gifFigure 56. Preferred Asymptotic Graph

The poles and zeros are calculated assuming C2 >> C1 and R1 >> R3. This assumption is correct because the C1 and R3 components set the high frequencies.

This TLV226x-Q1 device type-3 compensation circuit design boosts the gain and phase for the DC-to-DC converter around 30-KHz resonance frequencies. This corresponds to 1 µH and 22 µF for the output filter.

The operational amplifier is configured as type-2 compensation by omitting the C3 capacitor. Type-2 compensates the DC-to-DC converter with an output capacitor with a series resistor ESR; see Equation 3.

Equation 3. TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463-Q1 TLV2463A-Q1 TLV2464A-Q1 pe2compgain_gls008.gif